IS25C04-2ZI-TR ISSI, Integrated Silicon Solution Inc, IS25C04-2ZI-TR Datasheet - Page 4

• Manufacturer Part Number: IS25C04-2ZI-TR
• Description: IC EEPROM 4KBIT 10MHZ 8TSSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS25C04-2ZI-TR

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8)
• Speed: 2MHz, 5MHz, 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 1. Status Register Format
Bit 7
STATUS REGISTER
Notes:
1. X = Don't care bit.
2. During internal write cycles, bits 0 to 7 are temporarily 1's.
Write Enable (WEN), Bit 1: This bit represents the
status of device write protection. If WEN = 0, the Status
Register and the entire array is protected from modifica-
tion, regardless of the setting of WP pin or block protec-
tion. The only way to set WEN to 1 is via the Write
Enable command (WREN). WEN is reset to 0 upon
power-up, successful completion of Write, WRDI,
WRSR, or WP being Low.
4
The status register contains 8-bits for write protection
control and write status. (See Table 1). It is the only
region of memory other than the main array that is
accessible by the user.
The Status Register is Read-Only if either: a) Hardware
Write Protection is enabled or b) WEN is set to 0. If
neither is true, it can be modified by a valid instruction.
Ready (RDY
the device is busy with a write cycle. RDY = 0 indi-
cates that the device is ready for an instruction. If RDY
= 1, the only command that will be handled by the
device is Read Status Register.
IS25C02
IS25C04
X
Bit 6 Bit 5 Bit 4
RDY
RDY
RDY), Bit 0: When RDY = 1, it indicates that
RDY
X
X
X
Bit 3 Bit 2
BP1 BP0 WEN RDY
Bit1 Bit 0
Block Protect (BP1, BP0), Bits 2-3: Together, these
bits represent one of four block protection configurations
implemented for the memory array. (See Table 2 for
details.)
BP0 and BP1 are non-volatile cells similar to regular
array cells, and factory programmed to 0. The block of
memory defined by these bits is always protected,
regardless of the setting of WP or WEN.
Table 2. Block Protection
Level
0
1(1/4)
2(1/2)
3(All)
Don’t Care, Bits 4-7: Each of these bits can receive
either 0 or 1, but values will not be retained. When
these bits are read from the register, they are always 0.
Integrated Silicon Solution, Inc. — 1-800-379-4774
BP1
Register
Status
0
0
1
1
Bits
BP0
0
1
0
1
Array Addresses Protected
IS25C02
None
-FFh
-FFh
-FFh
Preliminary Information Rev. 00F
C0h
80h
00h
ISSI
IS25C04
-1FFh
-1FFh
-1FFh
None
180h
100h
000h
12/22/05
®