UPD44646363AF5-E25-FQ1 Renesas Electronics America, UPD44646363AF5-E25-FQ1 Datasheet - Page 9

• Manufacturer Part Number: UPD44646363AF5-E25-FQ1
• Description: SRAM DDRII 72MBIT 165-PBGA
• Manufacturer: Renesas Electronics America

Specifications of UPD44646363AF5-E25-FQ1

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II+
• Memory Size: 72M (2M x 36)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power-On Sequence in DDR II+ SRAM
can be applied simultaneously, as long as V
following power-down supply voltage removal sequence is recommended: V
can be removed simultaneously, as long as V
The following timing charts show the recommended power-on sequence.
Power-On Sequence
DLL/PLL Constraints
ODT initialization
Power-On Waveforms
V
DDR II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
The following power-up supply voltage application is recommended: V
DD
Apply power and tie DLL# to HIGH.
Select ODT ON/OFF.
Provide stable clock for more than 20
The DLL/PLL uses K clock as its synchronizing input and the input should have low phase jitter which is specified
as TKC var. The DLL/PLL can cover 190 MHz as the lowest frequency. If the input clock is unstable and the
DLL/PLL is enabled, then the DLL/PLL may lock onto an undesired clock frequency.
The ODT ON/OFF is set at power-on sequence. When the ODT Control pin is HIGH before applying stable clock,
the ODT function is turn on. When the ODT Control pin is LOW or No Connect, the ODT function is off. The ODT
can not change the state after power-on.
- Apply V
- Apply V
/V
Clock
DLL#
ODT
DD
Q
DD
DD
Q before V
before V
μ
PD44646092A-A, 44646182A-A, 44646362A-A, 44646093A-A, 44646183A-A, 44646363A-A
Unstable Clock
DD
REF
Q.
or at the same time as V
V
Fix HIGH or LOW (or No Connect)
DD
Fix HIGH (or tied to V
Preliminary Data Sheet M19960EJ1V0DS
μ
/V
s to lock the DLL/PLL.
DD
DD
DD
Q Stable (< ±0.1 V DC per 50 ns)
Q does not exceed V
Q does not exceed V
REF.
DD
Q)
20 μs or more
Stable Clock
DD
DD
by more than 0.5 V during power-up. The
by more than 0.5 V during power-down.
SS
, V
IN
DD
, V
, V
REF
DD
, V
Q, V
DD
REF
Q, V
, then V
DD
, V
SS
Normal Operation
Start
IN
. V
. V
DD
DD
and V
and V
DD
DD
Q
Q
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