DS28E04S-100+T Maxim Integrated Products, DS28E04S-100+T Datasheet - Page 9

• Manufacturer Part Number: DS28E04S-100+T
• Description: IC EEPROM 4KBIT 16SOIC
• Manufacturer: Maxim Integrated Products

Specifications of DS28E04S-100+T

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (256 x 16)
• Interface: 1-Wire Serial
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Speed: -

PIO-RELATED REGISTERS
Figure 6 shows the simplified logic diagram of a PIO channel. The registers related to the PIO pins are located in
the address range 0220h to 0225h. All these registers are volatile, i.e., they lose their state when the device is
powered down. All PIO-related registers can be read like any data memory. There are special commands to control
the PIOs for input (read), output (write), pulse-generation, and to reset the activity latches.
Figure 6. PIO Simplified Logic Diagram
PIO Logic State Register
The logic state of the PIO pins can be obtained by reading this register using the Read Memory command. This
register is read-only. Each bit is associated with the pin of the respective PIO channel. Bits 2 to 7 have no function;
they always read 1. The data in this register reflects the PIO state at the last (most significant) bit of the byte that
proceeds reading the first (least significant) bit of this register. See the PIO Access Read command description for
details.
PIO Output Latch State Register
The data in this register represents the latest data written to the PIOs through the PIO Access Write command.
This register is read using the Read Memory command. This register is not affected if the device re-initializes itself
after an ESD hit. This register is read-only. Each bit is associated with the output latch of the respective PIO
channel. Bits 2 to 7 have no function; they always read 1. The flip-flops of this register power up as specified by the
state of the POL pin. If the chip has to power up with all PIO channels off, the POL pin must be connected to a logic
"1".
ADDR
0220h
ADDR
0221h
b7
b7
1
1
To PIO Output
Latch State Reg.
To PIO Logic
State Register
To Activity Latch
State Register
POWER ON
RESET
CLR ACT LATCH
b6
b6
Function
Control
1
1
Port
b5
b5
1
1
b4
b4
1
1
CLOCK
DATA
b3
b3
1
1
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PIO Activity
Latch
PIO Output
Latch
Q
D
Q
b2
b2
1
1
R
Q
D
Q
"1"
Detector
PL1
P1
b1
b1
Edge
PL0
b0
P0
b0
P0, P1