DS28E04S-100+T Maxim Integrated Products, DS28E04S-100+T Datasheet - Page 29

• Manufacturer Part Number: DS28E04S-100+T
• Description: IC EEPROM 4KBIT 16SOIC
• Manufacturer: Maxim Integrated Products

Specifications of DS28E04S-100+T

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (256 x 16)
• Interface: 1-Wire Serial
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Speed: -

Master-to-Slave
For a write-one time slot, the voltage on the data line must have crossed the V
low time t
threshold until the write-zero low time t
data line should not exceed V
the DS28E04-100 needs a recovery time t
Slave-to-Master
A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below V
read low time t
data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again.
When responding with a 1, the DS28E04-100 does not hold the data line low at all, and the voltage starts rising as
soon as t
The sum of t
define the master sampling window (t
For the most reliable communication, t
but no later than t
guarantees sufficient recovery time t
specified herein applies only to a single DS28E04-100 attached to a 1-Wire line. For multidevice configurations,
t
interface that performs active pullup during the 1-Wire recovery time such as the DS2482-x00 or DS2480B 1-Wire
line drivers can be used.
IMPROVED NETWORK BEHAVIOR (SWITCHPOINT HYSTERESIS)
In a 1-Wire environment, line termination is possible only during transients controlled by the bus master (1-Wire
driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the physical size and
topology of the network, reflections from end points and branch points can add up, or cancel each other to some
extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. Noise coupled onto the
1-Wire line from external sources can also result in signal glitching. A glitch during the rising edge of a time slot can
cause a slave device to lose synchronization with the master and, consequently, result in a search ROM command
coming to a dead end or cause a device-specific function command to abort. For better performance in network
applications, the DS28E04-100 uses a new 1-Wire front end, which makes it less sensitive to noise and also
reduces the magnitude of noise injected by the slave device itself.
The 1-Wire front end of the DS28E04-100 differs from traditional slave devices in four characteristics.
1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the line
2) There is additional lowpass filtering in the circuit that detects the falling edge at the beginning of a time slot.
3) There is a hysteresis at the low-to-high switching threshold V
4) There is a time window specified by the rising edge hold-off time t
Only devices that have the parameters t
improved 1-Wire front end.
REC
impedance than a digitally switched transistor, converting the high-frequency ringing known from traditional
devices into a smoother low-bandwidth transition. The slew-rate control is specified by the parameter t
which has different values for standard and Overdrive speed.
This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at Overdrive speed.
below V
they extend below V
appear late after crossing the V
taken as the beginning of a new time slot (Figure 17, Case C, t
needs to be extended to accommodate the additional 1-Wire device input capacitance. Alternatively, an
RL
W1LMAX
is over.
TH
RL
- V
RL
+ d (rise time) on one side and the internal timing generator of the DS28E04-100 on the other side
is expired. During the t
HY
is expired. For a write-zero time slot, the voltage on the data line must stay below the V
, it will not be recognized (Figure 17, Case A). The hysteresis is effective at any 1-Wire speed.
MSRMAX
TH
. After reading from the data line, the master must wait until t
- V
ILMAX
HY
threshold (Figure 17, Case B, t
during the entire t
TH
MSRMIN
REC
threshold and extend beyond the t
RL
W0LMIN
RL
for the DS28E04-100 to get ready for the next time slot. Note that t
REC
should be as short as permissible, and the master should read close to
FPD
window, when responding with a 0, the DS28E04-100 starts pulling the
to t
before it is ready for the next time slot.
, V
is expired. For the most reliable communication, the voltage on the
MSRMAX
HY
, and t
W0L
29 of 36
) in which the master must perform a read from the data line.
or t
REH
W1L
specified in their electrical characteristics use the
window. After the V
TH
GL
GL
. If a negative glitch crosses V
³ t
< t
REH
REH
REH
REH
during which glitches are ignored, even if
).
). Deep voltage droops or glitches that
window cannot be filtered out and are
TH
TH
threshold before the write-one
threshold has been crossed,
SLOT
TH
is expired. This
but does not go
TL
until the
FPD
REC
TH
,