CY62177EV30LL-55ZXI Cypress Semiconductor Corp, CY62177EV30LL-55ZXI Datasheet

IC SRAM 32MBIT 55NS LP 48-TSOP

CY62177EV30LL-55ZXI

Manufacturer Part Number
CY62177EV30LL-55ZXI
Description
IC SRAM 32MBIT 55NS LP 48-TSOP
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY62177EV30LL-55ZXI

Memory Size
32M (4Mx8, 2Mx16)
Package / Case
48-TSOP I
Format - Memory
RAM
Memory Type
SRAM
Speed
55ns
Interface
Parallel
Voltage - Supply
2.2 V ~ 3.7 V
Operating Temperature
-40°C ~ 85°C
Access Time
55 ns
Supply Voltage (max)
3.7 V
Supply Voltage (min)
2.2 V
Maximum Operating Current
45 mA
Organization
2 M x 16, 4 M x 8
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY62177EV30LL-55ZXI
Manufacturer:
XILINX
Quantity:
1 000
Part Number:
CY62177EV30LL-55ZXI
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Part Number:
CY62177EV30LL-55ZXI
0
Features
Note
Cypress Semiconductor Corporation
Document #: 001-09880 Rev. *D
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
TSOP I Configurable as 2M x 16 or as 4M x 8 SRAM
Very High Speed
Wide Voltage Range
Ultra Low Standby Power
Ultra Low Active Power
Easy Memory Expansion with CE
Automatic Power Down when Deselected
CMOS for Optimum Speed and Power
Available in Pb-Free 48-Ball FBGA and TSOPI Package
55 ns
2.2V to 3.7V
Typical Standby Current: 3 μA
Maximum Standby Current: 25 μA
Typical Active Current: 4.5 mA at f = 1 MHz
A
A
A
A
A
A
A
A
A
A
A
1
10
, CE
9
8
7
6
5
4
3
2
1
0
2,
and OE Features
Power- Down
198 Champion Court
Circuit
COLUMN DECODER
DATA IN DRIVERS
RAM Array
2M × 16
32 Mbit (2M x 16 / 4M x 8) Static RAM
Functional Description
The CY62177EV30 is a high performance CMOS static RAM
organized as 2M words by 16 bits and 4M words by 8 bits
device features advanced circuit design to provide ultra low
active current. It is ideal for providing More Battery Life™
(MoBL
The device also has an automatic power down feature that signif-
icantly reduces power consumption by 99 percent when
addresses are not toggling. The device can also be put into
standby mode when deselected (CE
BHE and BLE are HIGH). The input and output pins (IO
IO
(CE
Byte High Enable and Byte Low Enable are disabled (BHE, BLE
HIGH), or during a write operation (CE
WE LOW).
To write to the device, take Chip Enables (CE
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (IO
written into the location specified on the address pins (A
A
(IO
address pins (A
Chip Enables (CE
(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins appear on IO
Enable (BHE) is LOW, then data from memory appears on IO
to IO
of read and write modes.
Pin #13 of the 48 TSOP1 package is a DNU pin that must be left
floating at all times to ensure proper application
20
15
8
). If Byte High Enable (BHE) is LOW, then data from I/O pins
1
) are placed in a high impedance state when: deselected
15
BHE
HIGH or CE
BLE
through IO
®
. See the
) in portable applications such as cellular telephones.
San Jose
15
Truth Table
0
2
) is written into the location specified on the
through A
LOW), outputs are disabled (OE HIGH), both
1
IO
IO
OE
BLE
BYTE
LOW and CE
BHE
WE
,
0
8
–IO
–IO
CA 95134-1709
7
15
CE
CE
CY62177EV30 MoBL
2
1
on page 9 for a complete description
20
). To read from the device, take
CE
CE
Revised September 18, 2009
2
2
1
1
HIGH) and Output Enable
HIGH or CE
1
LOW, CE
0
to IO
0
1
through IO
.
LOW and CE
408-943-2600
2
7
. If Byte High
LOW or both
2
HIGH and
0
0
through
through
[1]
. This
7
), is
®
2
8
[+] Feedback

Related parts for CY62177EV30LL-55ZXI

CY62177EV30LL-55ZXI Summary of contents

Page 1

... A 0 Note 1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 001-09880 Rev Mbit ( Static RAM Functional Description The CY62177EV30 is a high performance CMOS static RAM organized as 2M words by 16 bits and 4M words by 8 bits device features advanced circuit design to provide ultra low active current ideal for providing More Battery Life™ ...

Page 2

... Product V Range (V) CC [6] Min Typ CY62177EV30LL 2.2 3.0 Notes 2. Ball E3 for the FBGA package is used to upgrade to a 64M density pins are not connected on the die. 4. DNU Pin# 13 needs to be left floating to ensure proper application. 5. The BYTE pin in the 48-TSOPI package has to be tied to V tying the BYTE signal to V ...

Page 3

... CMOS levels to meet the Document #: 001-09880 Rev Input Voltage Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA Operating Range Device + 0.3V CC(max) CY62177EV30LL + 0.3V CC (max) Test Conditions I = –0 2.20V –1 ...

Page 4

Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description Θ Thermal Resistance Still Air, soldered × 4.5 inch, JA (Junction to Ambient) 2-layer printed circuit board Θ Thermal ...

Page 5

... HZCE HZBE HZWE 18. The internal Write time of the memory is defined by the overlap of WE, CE and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 001-09880 Rev. *D ...

Page 6

Switching Waveforms Figure 5. Read Cycle 1 (Address Transition Controlled) ADDRESS PREVIOUS DATA VALID DATA OUT ADDRESS ACE / BHE BLE t LZBE OE t LZOE HIGH IMPEDANCE DATA OUT t LZCE ...

Page 7

Switching Waveforms (continued) Figure 7. Write Cycle 1 (WE Controlled) ADDRESS BHE BLE OE DATA IO NOTE 24 t HZOE Figure 8. Write Cycle 2 (CE ADDRESS ...

Page 8

Switching Waveforms (continued) Figure 9. Write Cycle 3 (WE Controlled, OE LOW) ADDRESS BHE BLE DATA IO NOTE 24 Figure 10. Write Cycle 4 (BHE/BLE Controlled, OE LOW) ADDRESS ...

Page 9

... Ordering Information Speed (ns) Ordering Code 55 CY62177EV30LL-55BAXI CY62177EV30LL-55ZXI Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Document #: 001-09880 Rev. *D BLE Inputs Outputs X High Z X High Z H High Z L Data Out (IO – High Z (IO –IO ...

Page 10

Package Diagrams TOP VIEW A1 CORNER 8.00±0.10 SEATING PLANE C Document #: 001-09880 Rev. *D Figure 11. 48-Ball FBGA (8 x 9.5 x 1.2 mm) ...

Page 11

Package Diagrams (continued) DIMENSIONS IN INCHES[MM] MIN. MAX. JEDEC # MO-142 1 0.004[0.10] 0.008[0.21] 0°-5° Document #: 001-09880 Rev. *D Figure 12. 48-Pin TSOP I ( mm) N 0.472[12.00] 0.724 [18.40] 0.047[1.20] 0.787[20.00] 0.010[0.25] GAUGE PLANE ...

Page 12

Document History Page Document Title: CY62177EV30 MoBL Document Number: 001-09880 Orig. of Revision ECN Change ** 498562 NXR *A 2544845 VKN/PYRS *B 2589750 VKN/PYRS *C 2668432 VKN/PYRS *D 2779867 VKN Document #: 001-09880 Rev. *D ® 32 Mbit (2M x ...

Page 13

... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...

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