CY7C1371D-100AXC Cypress Semiconductor Corp, CY7C1371D-100AXC Datasheet - Page 9

• Manufacturer Part Number: CY7C1371D-100AXC
• Description: IC SRAM 18MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1371D-100AXC

• Memory Size: 18M (512K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 8.5 ns
• Maximum Clock Frequency: 100 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 175 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Memory Configuration: 1M X 18 / 512K X 36
• Clock Frequency: 100MHz
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Density: 18Mb
• Access Time (max): 8.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 175mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1631

Pin Definitions
Document Number: 38-05556 Rev. *I
A
BW
BW
WE
ADV/LD
CLK
CE
CE
CE
OE
CEN
ZZ
DQ
DQP
MODE
V
V
V
0
DD
DDQ
SS
, A
1
2
3
Name
s
A
C
, BW
X
, BW
1
, A
B
D
Input strap pin Mode input. Selects the burst order of the device.
asynchronous
asynchronous
Power supply Power supply inputs to the core of the device.
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
Input-clock
IO power
Ground
supply
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
IO-
IO-
IO
Address inputs used to select one of the address locations. Sampled at the rising edge of the
CLK. A
Byte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK.
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/load input. Used to advance the on-chip address counter or load a new address. When
HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After being deselected, ADV/LD must be
driven LOW to load a new address.
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK
is only recognized if CEN is active LOW.
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Output enable, asynchronous input, active LOW. Combined with the synchronous logic block
inside the device to control the direction of the IO pins. When LOW, the IO pins are allowed to
behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE
is masked during the data portion of a write sequence, during the first clock when emerging from
a deselected state, when the device has been deselected.
Clock enable input, active LOW. When asserted LOW the Clock signal is recognized by the
SRAM. When deasserted HIGH the Clock signal is masked. While deasserting CEN does not
deselect the device, use CEN to extend the previous cycle when required.
ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.
Bidirectional data IO lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the
pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH,
DQ
the data portion of a write sequence, during the first clock when emerging from a deselected state,
and when the device is deselected, regardless of the state of OE.
Bidirectional data parity IO lines. Functionally, these signals are identical to DQ
When tied to Gnd selects linear burst sequence. When tied to V
burst sequence.
Power supply for the IO circuitry.
Ground for the device.
2
1
1
s
and CE
and DQP
and CE
and CE
[1:0]
are fed to the two-bit burst counter.
3
2
3
to select/deselect the device.
to select/deselect the device.
[A:D]
to select/deselect the device.
are placed in a tri-state condition.The outputs are automatically tri-stated during
Description
DD
or left floating selects interleaved
CY7C1371D
CY7C1373D
s
.
Page 9 of 33
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