CY7C1371D-100AXC Cypress Semiconductor Corp, CY7C1371D-100AXC Datasheet - Page 16

• Manufacturer Part Number: CY7C1371D-100AXC
• Description: IC SRAM 18MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1371D-100AXC

• Memory Size: 18M (512K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 8.5 ns
• Maximum Clock Frequency: 100 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 175 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Memory Configuration: 1M X 18 / 512K X 36
• Clock Frequency: 100MHz
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Density: 18Mb
• Access Time (max): 8.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 175mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1631

TAP AC Switching Characteristics
Over the Operating Range
Notes
Document Number: 38-05556 Rev. *I
Clock
t
t
t
t
Output Times
t
t
Setup Times
t
t
t
Hold Times
t
t
t
10. t
11. Test conditions are specified using the load in TAP AC test Conditions. t
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
Parameter
CS
and t
CH
refer to the setup and hold time requirements of latching data from the boundary scan register.
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
TMS setup to TCK clock rise
TDI setup to TCK clock rise
Capture setup to TCK rise
TMS Hold after TCK clock rise
TDI Hold after clock rise
Capture hold after clock rise
[10, 11]
Description
R
/t
F
= 1 ns.
Min
50
20
20
–
–
0
5
5
5
5
5
5
Max
20
10
–
–
–
–
–
–
–
–
–
–
CY7C1371D
CY7C1373D
Page 16 of 33
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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