N25Q128A13BF840F NUMONYX, N25Q128A13BF840F Datasheet - Page 39

• Manufacturer Part Number: N25Q128A13BF840F
• Description: IC SRL FLASH 128MB NMX 8-VDFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of N25Q128A13BF840F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

N25Q128 - 3 V
Table 5.
6.3.1
Note:
6.3.2
6.3.3
Table 6.
VCR<1:0>
0
1
15
31
63
Starting Address
Volatile Configuration Register
Dummy clock cycle: VCR bits 7 to 4
Bits 7 to 4 of the Volatile Configuration Register, like bits 15 to 12 of the Non-Volatile
Configuration register, set the dummy clock cycles number after the fast read instructions (in
all the 3 available protocols). The dummy clock cycles number can be set from 1 to 15
according to operating frequency as described the Volatile Configuration Register.
If the dummy clock number is not sufficient for the operating frequency, the memory reads
wrong data.
XIP Volatile Configuration bits (VCR bit 3)
The bit 3 of the Volatile Configuration Register is the XIP enabling bit, this bit must be set to
0 to enable the memory working on XIP mode. For devices with a feature set digit equal to 2
or 4 in the part number (Basic XiP), this bit is always Don't Care, and it is possible to operate
the memory in XIP mode without setting it to 0. See
Wrap: VCR bits 1:0
The bits from 1 to 0 of the Volatile Configuration Register allow the Wrap mode to be
available for each kind of read instruction and protocol. A specific setting provides the ability
to read the memory from sequentially (standard) mode to a wrap mode, where the reads
can be confined inside the 16, 32, or 64 byte boundary. For Wrap setting options, see
5.: Volatile Configuration
of bytes in the 16-byte, 32-byte, and 64-byte options, according to the starting address.
Sequence of Bytes Read during Wrap Mode
Wrap
0-1-2- . . . -15-0-1- . .
1-2- . . . -15-0-1-2- . .
15-0-1-2-3- . . . -15-0-1- . .
31-16-17- . . . -31-16-17- . .
63-48-49- . . . -63-48-49- . .
16-Byte Wrap
00
01
10
11
Register. The following table shows an example of the sequence
0
1
2
3
0-1-2- . . . -31-0-1- . .
1-2- . . . -31-0-1-2- . .
15-16-17- . . . -31-0-1- . .
31-0-1-2-3- . . . -31-0-1- . .
63-32-33- . . . -63-32-33- . .
Micron Technology, Inc., reserves the right to change products or specifications without notice.
32-Byte Wrap
16-byte wrap: Output data wraps within an
aligned 16-byte boundary starting from the
address issued after the command code.
32-byte wrap: Output data wraps within an
aligned 32-byte boundary starting from the
address issued after the command code.
64-byte wrap: Output data wraps within an
aligned 64-byte boundary starting from the
address issued after the command code.
Continous reading (Default): All bytes are read
sequentially
Section 16: Ordering
Volatile and Non Volatile Registers
©2010 Micron Technology, Inc. All rights reserved.
0-1-2- . . . -63-0-1- . .
1-2- . . . -63-0-1-2- . .
15-16-17- . . . -63-0-1- . .
31-32-33- . . . -63-0-1- . .
63-0-1- . . . -63-0-1- . .
64-Byte Wrap
information.
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