M29W800DT70N6F NUMONYX, M29W800DT70N6F Datasheet - Page 12

• Manufacturer Part Number: M29W800DT70N6F
• Description: IC FLASH 8MBIT 70NS 48TSOP
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29W800DT70N6F

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 8M (1M x 8 or 512K x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 10mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Signal descriptions
See
connected to this device.
Address inputs (A0-A18)
The address inputs select the cells in the memory array to access during bus read
operations. During bus write operations they control the commands sent to the command
interface of the internal state machine.
Data inputs/outputs (DQ0-DQ7)
The data inputs/outputs output the data stored at the selected address during a bus read
operation. During bus write operations they represent the commands sent to the command
interface of the internal state machine.
Data inputs/outputs (DQ8-DQ14)
The data inputs/outputs output the data stored at the selected address during a bus read
operation when BYTE is High, V
high impedance. During bus write operations the command register does not use these bits.
When reading the status register these bits should be ignored.
Data input/output or address input (DQ15A-1)
When BYTE is High, V
BYTE is Low, V
the word on the other addresses, DQ15A–1 High will select the MSB. Throughout the text
consider references to the data input/output to include this pin when BYTE is High and
references to the address inputs to include this pin when BYTE is Low except when stated
explicitly otherwise.
Chip enable (E)
The chip enable, E, activates the memory, allowing bus read and bus write operations to be
performed. When Chip Enable is High, V
Output enable (G)
The output enable, G, controls the bus read operation of the memory.
Figure 1: Logic diagram
IL
, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of
IH
, this pin behaves as a data input/output pin (as DQ8-DQ14). When
and
IH
Table 1: Signal names
. When BYTE is Low, V
IH
, all other pins are ignored.
for a brief overview of the signals
IL
, these pins are not used and are