M25PE16-VMW6TG NUMONYX, M25PE16-VMW6TG Datasheet - Page 37

• Manufacturer Part Number: M25PE16-VMW6TG
• Description: IC FLASH 16MBIT 75MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25PE16-VMW6TG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (2M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Package: 8SOIC W
• Cell Type: NOR
• Density: 16 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 64KByte x 32
• Timing Type: Synchronous
• Interface Type: Serial-SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25PE16-VMW6TGTR

M25PE16
6.12
Page erase (PE)
The page erase (PE) instruction sets to ‘1’ (FFh) all bits inside the chosen page. Before it
can be accepted, a write enable (WREN) instruction must previously have been executed.
After the write enable (WREN) instruction has been decoded, the device sets the write
enable latch (WEL).
The page erase (PE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on serial data input (D). Any address inside the
page is a valid address for the page erase (PE) instruction. Chip Select (S) must be driven
Low for the entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the page erase (PE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed page erase cycle (whose duration is t
While the page erase cycle is in progress, the status register may be read to check the value
of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed
page erase cycle, and is 0 when it is completed. At some unspecified time before the cycle
is complete, the write enable latch (WEL) bit is reset.
A page erase (PE) instruction applied to a page that is hardware or software protected is not
executed.
Any page erase (PE) instruction, while an erase, program or write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
If Reset (Reset) is driven Low while a page erase (PE) cycle is in progress, the page erase
cycle is interrupted and the programmed data may be corrupted (see
status after a Reset Low
a time of t
(S) Low. For the value of t
DC and AC
Figure 17. Page erase (PE) instruction sequence
1. Address bits A23 to A21 are don’t care.
RHSL
S
C
D
parameters.
is then required before the device can be re-selected by driving Chip Select
pulse). On Reset going Low, the device enters the reset mode and
0
RHSL
1
2
see
Instruction
3
Table 21: Timings after a Reset Low pulse
4
Figure
5
6
17.
7
MSB
23 22
8
9
24-bit address
2
29 30 31
1
0
Table 12: Device
AI04046
PE
in
Instructions
) is initiated.
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