M25P80-VMP6G NUMONYX, M25P80-VMP6G Datasheet - Page 33
![IC FLASH 8MBIT 75MHZ 8VFQFPN](/photos/19/5/190520/42268234_sml.jpg)
M25P80-VMP6G
Manufacturer Part Number
M25P80-VMP6G
Description
IC FLASH 8MBIT 75MHZ 8VFQFPN
Manufacturer
NUMONYX
Series
Forté™r
Specifications of M25P80-VMP6G
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
8M (1M x 8)
Speed
75MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-VFQFN, 8-VFQFPN
Clock Frequency
50MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
VFQFPN
No. Of Pins
8
Base Number
25
Frequency
75MHz
Ic Generic
RoHS Compliant
Memory Configuration
1M X 8
Interface Type
Serial, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M25P80-VMP6G
Manufacturer:
ST
Quantity:
20 000
6.11
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the Deep Power-down mode). It can also be used as an extra
software protection mechanism, while the device is not in active use, since in this mode, the
device ignores all Write, Program and Erase instructions.
Driving Chip Select (S) High deselects the device, and puts the device in the Standby mode
(if there is no internal cycle currently in progress). But this mode is not the Deep Power-
down mode. The Deep Power-down mode can only be entered by executing the Deep
Power-down (DP) instruction, to reduce the standby current (from I
in
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down and Read Electronic Signature (RES)
instruction. This releases the device from this mode. The Release from Deep Power-down
and Read Electronic Signature (RES) instruction also allows the Electronic Signature of the
device to be output on Serial Data Output (Q).
The Deep Power-down mode automatically stops at Power-down, and the device always
Powers-up in the Standby mode.
The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as
Chip Select (S) is driven High, it requires a delay of t
to I
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 17. Deep Power-down (DP) instruction sequence
Table
S
C
D
CC2
and the Deep Power-down mode is entered.
14).
0
1
2
Instruction
3
4
5
6
Figure
7
17.
DP
Stand-by Mode
t
DP
before the supply current is reduced
CC1
Deep Power-down Mode
to I
CC2
, as specified
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