M25P80-VMP6G NUMONYX, M25P80-VMP6G Datasheet - Page 12

• Manufacturer Part Number: M25P80-VMP6G
• Description: IC FLASH 8MBIT 75MHZ 8VFQFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P80-VMP6G

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFQFN, 8-VFQFPN
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: VFQFPN
• No. Of Pins: 8
• Base Number: 25
• Frequency: 75MHz
• Ic Generic: RoHS Compliant
• Memory Configuration: 1M X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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4.4
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Operating features
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is
one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This
is followed by the internal Program cycle (of duration t
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see
and
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be
achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the
entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of
duration t
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase
(SE or BE) can be achieved by not waiting for the worst case delay (t
Write In Progress (WIP) bit is provided in the Status Register so that the application program
can monitor its value, polling it to establish when the previous Write cycle, Program cycle or
Erase cycle is complete.
Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is enabled, and in the Active Power mode.
When Chip Select (S) is High, the device is disabled, but could remain in the Active Power
mode until all internal cycles have completed (Program, Erase, Write Status Register). The
device then goes in to the Standby Power mode. The device consumption drops to I
The Deep Power-down mode is entered when the specific instruction (the Enter Deep
Power-down mode (DP) instruction) is executed. The device consumption drops further to
I
Deep Power-down mode and Read Electronic Signature (RES) instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This
can be used as an extra software protection mechanism, when the device is not in active
use, to protect the device from inadvertent Write, Program or Erase instructions.
CC2
. The device remains in this mode until another specific instruction (the Release from
Table 15: AC characteristics (75 MHz
SE
or t
BE
).
operation)).
PP
).
W
Page Program
, t
PP
, t
SE
, or t
BE
CC1
(PP),
). The
.