MT46V64M16TG-6T:A TR Micron Technology Inc, MT46V64M16TG-6T:A TR Datasheet - Page 52
![IC DDR SDRAM 1GBIT 6NS 66TSOP](/photos/7/22/72288/mfg557-66-tsop_sml.jpg)
MT46V64M16TG-6T:A TR
Manufacturer Part Number
MT46V64M16TG-6T:A TR
Description
IC DDR SDRAM 1GBIT 6NS 66TSOP
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V256M4P-6TA_TR.pdf
(82 pages)
Specifications of MT46V64M16TG-6T:A TR
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
1G (64M x 16)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Organization
64Mx16
Density
1Gb
Address Bus
16b
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
275mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
Data from any READ burst may be truncated with a BURST TERMINATE command, as
shown in Figure 29 on page 57. The BURST TERMINATE latency is equal to the CL, that
is, the BURST TERMINATE command should be issued x cycles after the READ
command where x equals the number of desired data element pairs (pairs are required
by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE
command can be issued. If truncation is necessary, the BURST TERMINATE command
must be used, as shown in Figure 30 on page 58. The
t
defined in the section on WRITEs.) A READ burst may be followed by, or truncated with,
a PRECHARGE command to the same bank provided that auto precharge was not acti-
vated.
The PRECHARGE command should be issued x cycles after the READ command, where
x equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 31 on page 59. Following the PRECHARGE
command, a subsequent command to the same bank cannot be issued until both
and
last data elements.
DQSS (MAX) case has a longer bus idle time. (
t
RP have been met. Part of the row precharge time is hidden during the access of the
52
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DQSS [MIN] and
1Gb: x4, x8, x16 DDR SDRAM
t
DQSS (NOM) case is shown; the
©2003 Micron Technology, Inc. All rights reserved.
t
DQSS [MAX] are
Operations
t
RAS