MT46V64M16TG-6T:A TR Micron Technology Inc, MT46V64M16TG-6T:A TR Datasheet - Page 24
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MT46V64M16TG-6T:A TR
Manufacturer Part Number
MT46V64M16TG-6T:A TR
Description
IC DDR SDRAM 1GBIT 6NS 66TSOP
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V256M4P-6TA_TR.pdf
(82 pages)
Specifications of MT46V64M16TG-6T:A TR
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
1G (64M x 16)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Organization
64Mx16
Density
1Gb
Address Bus
16b
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
275mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 17:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
AC Characteristics
Parameter
Access window of DQ from CK/CK#
CK high-level width
Clock cycle time
CK low-level width
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS–DQ skew, DQS to last DQ valid, per group, per access
WRITE command-to-first DQS latching transition
DQ and DM input setup time relative to DQS
DQS falling edge from CK rising – hold time
DQS falling edge to CK rising – setup time
Half-clock period
Data-out High-Z window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input pulse width (for each input)
Address and control input setup time (fast slew rate)
Address and control input setup time (slow slew rate)
Data-out Low-Z window from CK/CK#
LOAD MODE REGISTER command cycle time
DQ–DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE-to-READ with auto precharge command
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE/AUTO REFRESH command period
ACTIVE-to-READ or WRITE delay
REFRESH-to-REFRESH command interval
Average periodic refresh interval
AUTO REFRESH command period
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
Terminating voltage delay to V
DQS write preamble
DQS write preamble setup time
DQS write postamble
Electrical Characteristics and Recommended AC Operating Conditions (-75)
Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 26;
0°C ≤ T
A
≤ +70°C; V
DD
DD
Q = +2.5V ±0.2V, V
DD
= +2.5V ±0.2V
CL = 2.5
CL = 2
1Gb
1Gb
1Gb
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol
t
t
t
CK (2.5)
Electrical Specifications – DC and AC
t
t
t
t
t
DQSCK
WPRES
t
t
t
t
CK (2)
DQSQ
t
t
t
DQSH
WPRE
DIPW
t
t
t
t
t
t
WPST
DQSL
DQSS
t
t
t
t
MRD
REFC
t
RPRE
RPST
t
t
t
t
QHS
t
t
DSH
t
t
RAP
RCD
REFI
RRD
VTD
t
IPW
t
t
RAS
t
t
t
DSS
t
RFC
QH
DH
IH
IH
AC
CH
DS
HP
HZ
RC
CL
IS
IS
RP
LZ
F
S
F
S
t
1Gb: x4, x8, x16 DDR SDRAM
CH,
–0.75
–0.75
–0.75
t
t
Min
0.45
0.45
1.75
0.35
0.35
0.75
0.90
0.90
0.25
QHS
120
HP -
7.5
0.5
0.5
0.2
0.2
2.2
0.9
0.4
0.4
10
15
20
40
65
20
20
15
–
–
1
1
–
–
–
0
0
t
CL
-75
120,000
+0.75
+0.75
+0.75
Max
0.55
0.55
1.25
0.75
70.3
©2003 Micron Technology, Inc. All rights reserved.
0.5
7.8
1.1
0.6
0.6
13
13
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Units
t
t
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
Notes
27, 32
26, 27
27, 32
19, 43
19, 43
26, 27
21, 22
31
46
46
31
32
35
15
15
36
24
24
50
44
44
20