MT48LC64M8A2P-75:C Micron Technology Inc, MT48LC64M8A2P-75:C Datasheet - Page 50
![IC SDRAM 512MBIT 133MHZ 54TSOP](/photos/7/22/72261/557-54-tsop_sml.jpg)
MT48LC64M8A2P-75:C
Manufacturer Part Number
MT48LC64M8A2P-75:C
Description
IC SDRAM 512MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC64M8A2TG-75C_TR.pdf
(68 pages)
Specifications of MT48LC64M8A2P-75:C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (64M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Organization
64Mx8
Density
512Mb
Address Bus
15b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
115mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC64M8A2P-75:C
Manufacturer:
MITSUBISHI
Quantity:
450
Figure 34:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
DQML, DQMU
Power-Down Mode
COMMAND
Precharge all
BA0, BA1
A11, A12
active banks
A0–A9,
DQM/
CKE
CLK
A10
DQ
Note:
t CMS
High-Z
t CKS
t AS
SINGLE BANK
PRECHARGE
ALL BANKS
BANK(S)
T0
t CMH
t CKH
t AH
Violating refresh requirements during power-down may result in a loss of data.
Two clock cycles
All banks idle, enter
power-down mode
t CK
T1
NOP
t CKS
t CL
T2
NOP
Input buffers gated off while in
power-down mode
t CH
50
Exit power-down mode
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
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t CKS
Tn + 1
512Mb: x4, x8, x16 SDRAM
NOP
All banks idle
©2000 Micron Technology, Inc. All rights reserved.
Tn + 2
ACTIVE
ROW
ROW
BANK
Timing Diagrams
Don’t Care