MT48LC64M8A2P-75:C Micron Technology Inc, MT48LC64M8A2P-75:C Datasheet - Page 21
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MT48LC64M8A2P-75:C
Manufacturer Part Number
MT48LC64M8A2P-75:C
Description
IC SDRAM 512MBIT 133MHZ 54TSOP
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC64M8A2TG-75C_TR.pdf
(68 pages)
Specifications of MT48LC64M8A2P-75:C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (64M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Organization
64Mx8
Density
512Mb
Address Bus
15b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
115mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC64M8A2P-75:C
Manufacturer:
MITSUBISHI
Quantity:
450
Figure 8:
READs
Figure 9:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
Example Meeting
READ Command
COMMAND
READ bursts are initiated with a READ command, as shown in Figure 9.
The starting column and bank addresses are provided with the READ command, and
auto precharge either is enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst. For the
generic READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following CL after the READ command. Each subsequent data-out element
will be valid by the next positive clock edge. Figure 10 on page 22 shows general timing
for each possible CL setting.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
A0–A9, A11, A12: x4
RRD.
A0–A9, A11: x8
CLK
A11, A12: x16
A0–A9: x16
BA0, BA1
t
A12: x8
RCD (MIN) when 2 <
RAS#
CAS#
WE#
A10
CLK
CKE
CS#
ACTIVE
T0
HIGH
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
NOP
T1
ADDRESS
COLUMN
21
ADDRESS
BANK
t
RCD
t
RCD (MIN)/
Don't Care
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
NOP
t
CK ≤ 3
READ or
WRITE
512Mb: x4, x8, x16 SDRAM
T3
Don’t Care
©2000 Micron Technology, Inc. All rights reserved.
T4
Operations