MT46V128M4BN-5B:F Micron Technology Inc, MT46V128M4BN-5B:F Datasheet - Page 70
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MT46V128M4BN-5B:F
Manufacturer Part Number
MT46V128M4BN-5B:F
Description
IC DDR SDRAM 512MBIT 5NS 60FBGA
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V32M16P-5BF_TR.pdf
(91 pages)
Specifications of MT46V128M4BN-5B:F
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
512M (128Mx4)
Speed
5ns
Interface
Parallel
Voltage - Supply
2.5 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
60-FBGA
Organization
128Mx4
Density
512Mb
Address Bus
15b
Access Time (max)
700ps
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
2.6V
Package Type
FBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.5V
Supply Current
195mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT46V128M4BN-5B:F
Manufacturer:
MICRON
Quantity:
1 218
Company:
Part Number:
MT46V128M4BN-5B:F
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT46V128M4BN-5B:F
Manufacturer:
MICRON/镁光
Quantity:
20 000
Company:
Part Number:
MT46V128M4BN-5B:F TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 35:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
x4, x8 Data Output Timing –
Notes:
DQ (first data no longer valid)
DQ (first data no longer valid)
1.
2.
3. DQ transitioning after DQS transition define the
4. For a x4, only two DQ apply.
5.
6. The data valid window is derived for each DQS transitions and is defined as
All DQ and DQS collectively
t
t
transition, and ends with the last valid DQ transition.
T2n are an “early DQS”; at T3, a “nominal DQS”; and at T3n, a “late DQS”.
t
HP is the lesser of
DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
QH is derived from
DQ (last data valid)
DQ (last data valid)
DQS
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
CK#
CK
Earliest signal transition
3
6
Latest signal transition
T1
t
t
DQSQ,
CL or
t
HP:
t HP 1
t
t
QH =
CH clock transition collectively when a bank is active.
t
70
QH, and Data Valid Window
t
HP -
t HP 1
t DQSQ 2
t QH 5
t
QHS.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
window
Data
valid
T2
T2
T2
t HP 1
512Mb: x4, x8, x16 DDR SDRAM
T2n
t DQSQ 2
t
t QH 5
DQSQ window. DQS transitions at T2 and
window
t HP 1
T2n
T2n
Data
valid
T2n
T3
t QH 5
t DQSQ 2
©2000 Micron Technology, Inc. All rights reserved.
t HP 1
window
Data
valid
T3
T3
T3
T3n
t DQSQ 2
t QH 5
t HP 1
Operations
t
QH -
T4
window
T3n
T3n
Data
valid
t
T3n
DQSQ.