MT46V128M4BN-5B:F Micron Technology Inc, MT46V128M4BN-5B:F Datasheet - Page 33
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MT46V128M4BN-5B:F
Manufacturer Part Number
MT46V128M4BN-5B:F
Description
IC DDR SDRAM 512MBIT 5NS 60FBGA
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V32M16P-5BF_TR.pdf
(91 pages)
Specifications of MT46V128M4BN-5B:F
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
512M (128Mx4)
Speed
5ns
Interface
Parallel
Voltage - Supply
2.5 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
60-FBGA
Organization
128Mx4
Density
512Mb
Address Bus
15b
Access Time (max)
700ps
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
2.6V
Package Type
FBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.5V
Supply Current
195mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT46V128M4BN-5B:F
Manufacturer:
MICRON
Quantity:
1 218
Company:
Part Number:
MT46V128M4BN-5B:F
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT46V128M4BN-5B:F
Manufacturer:
MICRON/镁光
Quantity:
20 000
Company:
Part Number:
MT46V128M4BN-5B:F TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Table 23:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
AC Characteristics
Parameter
Access window of DQ from CK/CK#
CK high-level width
Clock cycle time
CK low-level width
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS–DQ skew, DQS to last DQ valid, per group, per access
WRITE command-to-first DQS latching transition
DQ and DM input setup time relative to DQS
DQS falling edge from CK rising – hold time
DQS falling edge to CK rising – setup time
Half-clock period
Data-out High-Z window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input pulse width (for each input)
Address and control input setup time (fast slew rate)
Address and control input setup time (slow slew rate)
Data-out Low-Z window from CK/CK#
LOAD MODE REGISTER command cycle time
DQ–DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE-to-READ with auto precharge command
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE/AUTO REFRESH command period
ACTIVE-to-READ or WRITE delay
REFRESH-to-REFRESH command interval
REFRESH-to-REFRESH command interval (Automotive)
Average periodic refresh interval
Average periodic refresh interval (Automotive)
AUTO REFRESH command period
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
Terminating voltage delay to V
DQS write preamble
DQS write preamble setup time
Electrical Characteristics and Recommended AC Operating Conditions (-75)
Notes: 1–6, 16–18, 34 apply to the entire table; Notes appear on page 35;
0°C ≤ T
A
≤ +70°C; V
DD
DD
Q = +2.5V ±0.2V, V
CL = 2.5
CL = 2
DD
= +2.5V ±0.2V
33
t
Symbol
t
t
t
CK (2.5)
t
t
t
t
t
DQSCK
REFC
WPRES
t
t
t
t
t
t
REFI
t
CK (2)
DQSH
DQSQ
WPRE
DIPW
t
t
t
t
t
t
DQSL
DQSS
t
t
t
t
RPRE
MRD
REFC
RPST
t
t
tr
t
t
DSH
t
t
t
t
QHS
RCD
REFI
RRD
VTD
t
IPW
t
t
RAP
RAS
t
t
t
DSS
t
DH
IH
IH
QH
AC
CH
HP
HZ
DS
IS
IS
RC
RP
CL
LZ
FC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
F
S
F
S
AT
AT
Electrical Specifications – DC and AC
t
HP -
t
CH,
512Mb: x4, x8, x16 DDR SDRAM
–0.75
–0.75
–0.75
Min
0.45
0.45
1.75
0.35
0.35
0.75
0.90
0.90
0.25
7.5
0.5
0.5
0.2
0.2
2.2
0.9
0.4
10
15
20
40
65
20
75
20
15
–
–
1
1
–
–
–
–
–
0
0
t
t
QHS
CL
-75
120,000
+0.75
+0.75
+0.75
17.55
Max
0.55
0.55
1.25
0.75
70.3
1.95
0.5
7.8
1.1
0.6
13
13
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
©2000 Micron Technology, Inc. All rights reserved.
Units
t
t
t
t
t
t
t
tCK
tCK
tCK
ns
CK
ns
ns
CK
ns
ns
ns
CK
CK
ns
CK
ns
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
ns
ns
ns
ns
ns
Notes
27, 32
26, 27
27, 32
19, 43
19, 43
26, 27
21, 22
31
46
46
31
32
35
15
15
36
24
24
24
24
50
44
44