IS43R32800B-5B ISSI, Integrated Silicon Solution Inc, IS43R32800B-5B Datasheet - Page 4

• Manufacturer Part Number: IS43R32800B-5B
• Description: IC DDR SDRAM 256MBIT 144BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS43R32800B-5B

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.4 V ~ 2.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IS43R32800B
4
PIN FUNCTIONS
/RAS , /CAS, /WE
V
CL K, /CLK
DDQ
V
DQS0- 3
DM0- 3
DQ0-31
SYMBOL
DD
BA 0,1
A0-1 1
CK E
Vref
/CS
, Vs s
, Vss
Q
Power Supp ly
Input / Output
Input / Output
Power Supp ly
TYPE
I nput
I nput
I nput
Input
Input
Input
Input
Input
V
Data Strobe: Outputwith read data, inputwith write data. E dge-aligned
with read data, centered in write data. Used to captu re write data.
DQS 0 for DQ0 - DQ7, DQS 1 for DQ8 - DQ15, DQS2 for DQ16 - DQ23,
DQS3 for DQ24 - DQ31.
Data Input/Output: D ata bus
DESCRIPTION
Cl ock: CL K a nd/CLK are differential clock inputs. A ll address and control
input signals are sampled on the crossing of the positive edge of CL K a nd
negative edgeof /CLK . Output (read) data is referenced to the crossings of
CL K a nd /CLK (both directions of crossing).
Cl ock E nable: CK E controls internal clock. W hen CKE is low, internal clock
for the following cycle is ceased. C KE is also used to select auto/ self refresh.
Af ter self refresh mode is started, CK E becomes asynchronous input. Self refresh
is maintained as long as CK E i s low.
Chip Select: W hen /CS is high, any command means No Operation.
Combination of /RA S, /CAS , /WE defines basic commands.
A0-1 1 specify the Row / Column Address in conjunction with BA0,1. T he
Row Address is specifi ed by A0-11. The Column Address is specified by
A0-7 ,A 9. A8 is also used to indicate precharge option. W hen A8 is
Bank Address: BA 0,1 specifies one of four banks to which a command is
appl i ed. BA 0,1 must be set with ACT, PR E, READ, WR IT E commands.
Power Supp ly for the memory array and peripheral circuitry.
DDQ
SST L_ 2 reference voltage.
Input Data Mask: DM is an inputmask signal for write data. I nput data
is masked when DM is sampled HIG H along with that input data
during a WR IT E access. DM is sampled on both edges of D QS.
Al though DM pins are input only, the DM loading matches the DQ
andDQS loading. DM 0 for DQ0 - DQ7, DM1 for DQ8 - DQ15,
DM 2 for DQ16 - DQ23, DM 3 for DQ24 - DQ31.
high at a read / write command, an auto precharge is performed. When A8
is high at a precharge command, all banks are precharged.
and Vss
Q
are suppl i ed to the Output Buffers only.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00D
03/19/08