IS42S32200E-6B-TR ISSI, Integrated Silicon Solution Inc, IS42S32200E-6B-TR Datasheet - Page 2

• Manufacturer Part Number: IS42S32200E-6B-TR
• Description: IC SDRAM 64MBIT 166MHZ 90BGA
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS42S32200E-6B-TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (2Mx32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IS42S32200E
GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V
memory systems containing 67,108,864 bits. Internally
configured as a quad-bank DRAM with a synchronous
interface. Each 16,777,216-bit bank is organized as 2,048
rows by 256 columns by 32 bits.
The 64Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK.
All inputs and outputs are LVTTL compatible.
The 64Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE
FUNCTIONAL BLOCK DIAGRAM
2
CKE
RAS
CAS
A10
CLK
BA0
BA1
WE
CS
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
GENERATOR
COMMAND
DECODER
11
CLOCK
&
ADDRESS
LATCH
ROW
ADDRESS BUFFER
BURST COUNTER
ADDRESS LATCH
REGISTER
MODE
COLUMN
COLUMN
11
Integrated Silicon Solution, Inc. — www.issi.com —
11
CONTROLLER
REFRESH
COUNTER
REFRESH
CONTROLLER
REFRESH
ADDRESS
BUFFER
SELF
ROW
function enabled. Precharge one bank while accessing one
of the other three banks will hide the precharge cycles and
provide seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A10 select the row). The READ or
WRITE commands in conjunction with address bits reg-
istered are used to select the starting column location for
the burst access.
Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations or full page, with a burst terminate
option.
BANK CONTROL LOGIC
11
2048
32
32
2048
2048
2048
DATA OUT
BUFFER
BUFFER
DATA IN
(x 32)
256
COLUMN DECODER
SENSE AMP I/O GATE
MEMORY CELL
BANK 0
32
32
ARRAY
DQM0-3
DQ 0-31
V
GND/GNDQ
DD
/V
DDQ
1-800-379-4774
Rev. 00D
06/02/08