EVAL6472PD STMicroelectronics, EVAL6472PD Datasheet - Page 31

• Manufacturer Part Number: EVAL6472PD
• Description: Power Management IC Development Tools L6472PD 7.0A w/SPI dSPIN 8 to 45V EVAL
• Manufacturer: STMicroelectronics
• Type: Motor / Motion Controllers & Driversr

Specifications of EVAL6472PD

• Product Category: Power Management IC Development Tools
• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: L6472PD
• Input Voltage: 8 V to 45 V
• Output Voltage: 8 V to 45 V
• Interface Type: SPI
• Output Current: 7 A
• For Use With: L6472

L6472
6.16
6.17
6.17.1
Internal voltage regulator
The L6472 integrates a voltage regulator which generates a 3 V voltage starting from motor
power supply (VSA and VSB). In order to make the voltage regulator stable, at least 22 µF
should be connected between the VREG pin and ground (the suggested value is 47 µF).
The internal voltage regulator can be used to supply the VDD pin in order to make the
device digital output range 3.3 V compatible
compatible can be obtained connecting the VDD pin to an external 5 V voltage source. In
both cases, a 10 µF capacitance should be connected to the VDD pin in order to obtain a
correct operation.
The internal voltage regulator is able to supply a current up to I
consumption included (I
can be supplied is I
If an external 3.3 V regulated voltage is available, it can be applied to the VREG pin in order
to supply all the internal logic and avoid power dissipation of the internal 3 V voltage
regulator
VREG pin.
Figure 14. Internal 3 V linear regulator
BUSY\SYNC pin
This pin is an open drain output which can be used as the busy flag or synchronization
signal according to the SYNC_EN bit value (STEP_MODE register).
BUSY operation mode
The pin works as busy signal when the SYNC_EN bit is set low (default condition). In this
mode the output is forced low while a constant speed, absolute positioning or motion
command is under execution. The BUSY pin is released when the command has been
executed (target speed or target position reached). The STATUS register includes a BUSY
flag that is the BUSY pin mirror (see
In the case of daisy chain configuration, BUSY pins of different ICs can be hard-wired to
save host controller GPIOs.
(Figure
14). The external voltage regulator should never sink current from the
REG
,
STBY
logic
). When the device is in standby mode the maximum current that
, internal consumption included (I
Doc ID 022729 Rev 2
Section
(Figure
9.1.19).
14). A digital output range 5 V
logic
REG,MAX
,
STBY
Functional description
).
, internal logic
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