IS61LV25616AL-10TL-TR ISSI, Integrated Silicon Solution Inc, IS61LV25616AL-10TL-TR Datasheet - Page 9

• Manufacturer Part Number: IS61LV25616AL-10TL-TR
• Description: IC SRAM 4MBIT 10NS 44TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61LV25616AL-10TL-TR

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 4M (256K x 16)
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TSOP II
• Density: 4Mb
• Access Time (max): 10ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 100mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Word Size: 16b
• Number Of Words: 256K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS61LV25616AL
AC WAVEFORMS
WRITE CYCLE NO. 1
WRITE CYCLE NO. 2
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. E
02/14/06
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of
2. WRITE = (CE)
the LB and UB inputs being in the LOW state.
ADDRESS
ADDRESS
[
(LB) = (UB)
UB, LB
UB, LB
D
D
OUT
WE
OUT
D
WE
D
CE
OE
CE
IN
IN
(CE Controlled, OE is HIGH or LOW)
(WE Controlled. OE is HIGH During Write Cycle)
LOW
]
t
(WE).
SA
DATA UNDEFINED
DATA UNDEFINED
t
SA
VALID ADDRESS
t
t
t
HZWE
AW
HZWE
t
VALID ADDRESS
AW
1-800-379-4774
t
t
t
t
PWE1
PWE2
PWE1
WC
t
t
SCE
WC
t
t
PBW
PBW
HIGH-Z
(1 )
HIGH-Z
t
t
SD
DATA
SD
DATA
IN
IN
VALID
VALID
(1,2)
t
t
HD
t
HD
t
LZWE
LZWE
t
t
HA
HA
UB_CEWR1.eps
UB_CEWR2.eps
ISSI
®
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