IS61LV25616AL-10TL-TR ISSI, Integrated Silicon Solution Inc, IS61LV25616AL-10TL-TR Datasheet - Page 8

• Manufacturer Part Number: IS61LV25616AL-10TL-TR
• Description: IC SRAM 4MBIT 10NS 44TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61LV25616AL-10TL-TR

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 4M (256K x 16)
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TSOP II
• Density: 4Mb
• Access Time (max): 10ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 100mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Word Size: 16b
• Number Of Words: 256K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB and WE LOW. All signals must be in
8
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = V
3. Address is valid prior to or coincident with CE LOW transition.
IS61LV25616AL
READ CYCLE NO. 2
Symbol
0V to 3.0V and output loading specified in Figure 1.
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold
timing are referenced to the rising or falling edge of the signal that terminates the write.
t
t
t
t
t
t
t
t
t
t
t
t
WC
SCE
AW
HA
SA
PWB
PWE
PWE
SD
HD
HZWE
LZWE
1
2
(2)
(2)
ADDRESS
Parameter
Write Cycle Time
CE to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
LB, UB
Current
Supply
D
V
OUT
OE
CE
DD
(1,3)
HIGH-Z
t
LZCE
t
LZB
t
PU
t
AA
50%
t
DOE
t
t
LZOE
t
ACE
Integrated Silicon Solution, Inc. — www.issi.com —
BA
t
IL
RC
.
Min. Max.
10
10
—
8
8
0
0
8
8
6
0
2
-10
(1,3)
t
RC
—
—
—
—
—
—
—
—
—
—
—
DATA VALID
(Over Operating Range)
5
Min. Max.
12
12
—
8
8
0
0
8
8
6
0
2
-12
t
HZCE
—
—
—
—
—
—
—
—
—
—
—
6
t
PD
t
t
t
OHA
HZB
HZOE
50%
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UB_CEDR2.eps
I
I
CC
SB
ISSI
1-800-379-4774
02/14/06
Rev. E
®