IS61LV256-12J ISSI, Integrated Silicon Solution Inc, IS61LV256-12J Datasheet

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IS61LV256-12J

Manufacturer Part Number
IS61LV256-12J
Description
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS61LV256-12J

Density
256Kb
Access Time (max)
12ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
15b
Package Type
SOJ
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
100mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.63V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
28
Word Size
8b
Number Of Words
32K
Lead Free Status / Rohs Status
Not Compliant

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ICSI
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IS61LV256
FEATURES
• High-speed access times:
• Automatic power-down when chip is deselected
• CMOS low power operation
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
• Three-state outputs
• Lead-free Available
FUNCTIONAL BLOCK DIAGRAM
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. K
06/06/05
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying
on any published information and before placing orders for products.
32K x 8 LOW VOLTAGE
CMOS STATIC RAM
-- 8, 10, 12, 15 ns
-- 345 mW (max.) operating
-- 7 mW (max.) CMOS standby
required
I/O0-I/O7
A0-A14
GND
VDD
CE
OE
WE
DECODER
CIRCUIT
CONTROL
CIRCUIT
DATA
I/O
DESCRIPTION
The
32,768-word by 8-bit static RAM. It is fabricated using
ISSI
reliable process coupled with innovative circuit design
techniques, yields access times as fast as 8 ns maximum.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation is reduced to
50 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Enable (CE). The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS61LV256 is available in the JEDEC standard 28-pin,
300-mil SOJ and the 450-mil TSOP (Type I) packages.
's high-performance CMOS technology. This highly
ISSI
MEMORY ARRAY
IS61LV256 is a very high-speed, low power,
COLUMN I/O
32K X 8
ISSI
June 2005
®
1

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IS61LV256-12J Summary of contents

Page 1

... CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61LV256 is available in the JEDEC standard 28-pin, 300-mil SOJ and the 450-mil TSOP (Type I) packages. DECODER I/O ...

Page 2

... IS61LV256 PIN CONFIGURATION 28-Pin SOJ A14 1 28 VDD WE A12 A13 A11 A10 I/O7 I/ I/O6 I/ I/O5 I/ I/O4 GND 14 15 I/O3 PIN DESCRIPTIONS A0-A14 Address Inputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Input/Output V Power DD GND Ground ABSOLUTE MAXIMUM RATINGS ...

Page 3

... IS61LV256 OPERATING RANGE Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH (1) V Input LOW Voltage IL I Input Leakage LI I Output Leakage LO Notes (min.) = – ...

Page 4

... IS61LV256 READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Output Hold Time OHA CE Access Time t ACE OE Access Time t DOE OE to Low-Z Output t (2) LZOE OE to High-Z Output t (2) HZOE CE to Low-Z Output t (2) LZCE CE to High-Z Output ...

Page 5

... IS61LV256 AC WAVEFORMS (1,2) READ CYCLE NO. 1 ADDRESS D OUT PREVIOUS DATA VALID (1,3) READ CYCLE NO. 2 ADDRESS LZCE HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE Address is valid prior to or coincident with CE LOW transitions. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...

Page 6

... IS61LV256 WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time Write End t SCE t Address Setup Time AW to Write End t Address Hold HA from Write End t Address Setup Time SA WE Pulse Width (OE HIGH) 6 PWE WE Pulse Width (OE LOW PWE t Data Setup to Write End SD t Data Hold from Write End ...

Page 7

... IS61LV256 (WE Controlled HIGH During Write Cycle) WRITE CYCLE NO. 2 ADDRESS OE CE LOW DATA UNDEFINED OUT D IN WRITE CYCLE NO. 3 (WE Controlled LOW During Write Cycle) ADDRESS OE LOW CE LOW DATA UNDEFINED OUT D IN Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write ...

Page 8

... Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 10 IS61LV256-10TI TSOP - Type I IS61LV256-10JI 300-mil Plastic SOJ 12 IS61LV256-12TI TSOP - Type I IS61LV256-12TLI TSOP - Type I, Lead-free IS61LV256-12JI 300-mil Plastic SOJ IS61LV256-12JLI 300-mil Plastic SOJ, Lead-free 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI ® Rev. K 06/06/05 ...

Page 9

PACKAGING INFORMATION 300-mil Plastic SOJ Package Code MILLIMETERS Sym. Min. Typ. Max. N0. Leads 24/26 A — — 3.56 A1 0.64 — — A2 2.41 — 2.67 b 0.41 — 0.51 B 0.66 — 0.81 ...

Page 10

PACKAGING INFORMATION 300-mil Plastic SOJ Package Code: J MILLIMETERS Sym. Min. Typ. Max. Min. Typ. Max. N0. Leads 28 A — — 3.56 — A1 0.64 — — 0.025 A2 2.41 — 2.67 0.095 b 0.41 — 0.51 0.016 B ...

Page 11

PACKAGING INFORMATION Plastic TSOP - 28-pins Package Code: T (Type Plastic TSOP (T—Type I) Millimeters Symbol Min Max Ref. Std. No. Leads A 1.00 1.20 A1 0.05 0.20 B 0.16 0.27 C 0.10 0.20 D 7.90 ...

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