ADP5062CP-EVALZ Analog Devices, ADP5062CP-EVALZ Datasheet - Page 6
![no-image](/images/manufacturer_photos/0/0/56/analog_devices_sml.jpg)
ADP5062CP-EVALZ
Manufacturer Part Number
ADP5062CP-EVALZ
Description
Power Management IC Development Tools ADP5062 Evaluation board
Manufacturer
Analog Devices
Type
Linear Regulators - Standardr
Series
ADP5062r
Datasheet
1.ADP5062CP-EVALZ.pdf
(44 pages)
Specifications of ADP5062CP-EVALZ
Rohs
yes
Product
Evaluation Boards
Tool Is For Evaluation Of
ADP5062
Input Voltage
4 V to 6.7 V
Description/function
Battery charger (isolated flyback)
Interface Type
I2C
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Output Current
2.1 A
Factory Pack Quantity
1
For Use With
ADP5062
ADP5062
Parameter
LOGIC INPUT PINS
1
2
3
4
5
RECOMMENDED INPUT AND OUTPUT CAPACITANCES
Table 2.
Parameter
CAPACITANCES
I
Table 3.
Parameter
I
1
2
2
2
Undervoltage lockout generated normally from ISO_Sx or ISO_Bx; in certain transition cases, it can be generated from VINx.
These values are programmable via I
The output current during charging may be limited by the input current limit or by the isothermal charging mode.
During weak charging mode, the charger provides at least 20 mA of charging current via the trickle charge branch to the battery unless trickle charging is disabled.
Any residual current that is not required by the system is also used to charge the battery.
Either JEITA1 (default) or JEITA2 can be selected in I
Guaranteed by design.
A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL (see Figure 2).
C-COMPATIBLE INTERFACE
C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS
Maximum Voltage on Digital Inputs
Maximum Logic Low Input Voltage
Minimum Logic High Input Voltage
Pull-Down Resistance
VINx
CBP
ISO_Sx
ISO_Bx
Capacitive Load for Each Bus Line
SCL Clock Frequency
SCL High Time
SCL Low Time
Data Setup Time
Data Hold Time
Setup Time for Repeated Start
Hold Time for Start/Repeated Start
Bus Free Time Between a Stop and a Start Condition
Setup Time for Stop Condition
Rise Time of SCL/SDA
Fall Time of SCL/SDA
Pulse Width of Suppressed Spike
1
2
2
C. Values are given with default register values.
Symbol
V
V
V
Symbol
C
C
C
C
DIN_MAX
IL
IH
VINx
CBP
ISO_Sx
ISO_Bx
2
C, or both JEITA functions can be enabled or disabled in I
Min
1.2
215
Min
4
6
10
10
Typ
10
22
22
Typ
350
Rev. 0 | Page 6 of 44
Max
5.5
0.5
610
Max
10
14
100
f
t
t
t
t
t
t
Symbol
C
t
t
t
t
t
SCL
HIGH
LOW
SU, DAT
HD, DAT
SU, STA
HD, STA
BUF
SU, STO
R
F
SP
S
Unit
V
V
V
kΩ
Unit
μF
nF
μF
μF
2
C.
Test Conditions/Comments
Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3
Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3
Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3
Applies to DIG_IO1, DIG_IO2, DIG_IO3
Test Conditions/Comments
Effective capacitance
Effective capacitance
Effective capacitance
Effective capacitance
Min
0.6
1.3
100
0
0.6
0.6
1.3
0.6
20
20
0
Typ
Max
400
400
0.9
300
300
50
Data Sheet
Unit
pF
kHz
µs
µs
ns
µs
µs
µs
µs
µs
ns
ns
ns