IS24C02B-2ZLI-TR ISSI, Integrated Silicon Solution Inc, IS24C02B-2ZLI-TR Datasheet - Page 9

• Manufacturer Part Number: IS24C02B-2ZLI-TR
• Description: IC EEPROM 2KBIT 1MHZ 8TSSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS24C02B-2ZLI-TR

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 400kHz, 1MHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Density: 2Kb
• Interface Type: Serial (2-Wire)
• Organization: 256x8
• Access Time (max): 400ns
• Frequency (max): 1MHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Supply Current: 3mA
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

GT24C02
DEVICE ADDRESSING
The Master begins a transmission on by sending a Start condition, and then sends the address of the
particular Slave devices to be communicated. The Slave device address is 8 bits format as shown in Fig. 5.
The four most significant bits of the Slave address are fixed (1010) for GT24C02.
The next three bits, A0, A1 and A2, of the Slave address are specifically related to EEPROM. Up to eight
GT24C02 units can be connected to the 2-wire bus.
The last bit of the Slave address specifies whether a Read or Write operation is to be performed. When this
bit is set to 1, Read operation is selected. While it is set to 0, Write operation is selected.
After the Master transmits the Start condition and Slave address byte appropriately, the associated 2-wire
Slave device, GT24C02, will respond with ACK on the SDA line. Then GT24C02 will pull down the SDA
on the ninth clock cycle, signaling that it received the eight bits of data.
The GT24C02 then prepares for a Read or Write operation by monitoring the bus.
WRITE OPERATION
Byte Write
In the Byte Write mode, the Master device sends the Start condition and the Slave address information
(with the R/W set to Zero) to the Slave device. After the Slave generates an ACK, the Master sends the byte
address that is to be written into the address pointer of the GT24C02. After receiving another ACK from the
Slave, the Master device transmits the data byte to be written into the address memory location. The
GT24C02 acknowledges once more and the Master generates the Stop condition, at which time the device
begins its internal programming cycle. While this internal cycle is in progress, the device will not respond
to any request from the Master device.
Page Write
The GT24C02 is capable of 16-byte Page-Write operation. A Page-Write is initiated in the same manner as
a Byte Write, but instead of terminating the internal Write cycle after the first data word is transferred, the
Master device can transmit up to 15 more bytes. After the receipt of each data word, the EEPROM responds
immediately with an ACK on SDA line, and the four lower order data word address bits are internally
incremented by one, while the higher order bits of the data word address remain constant. If a byte address
is incremented from the last byte of a page, it returns to the first byte of that page. If the Master device
should transmit more than 16 bytes prior to issuing the Stop condition, the address counter will “roll over,”
and the previously written data will be overwritten. Once all 16 bytes are received and the Stop condition
has been sent by the Master, the internal programming cycle begins. At this point, all received data is
written to the GT24C02 in a single Write cycle. All inputs are disabled until completion of the internal
Write cycle.
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage of the typical Write cycle time. Once the Stop
condition is issued to indicate the end of the host's Write operation, the GT24C02 initiates the internal
Write cycle. ACK polling can be initiated immediately. This involves issuing the Start condition followed
by the Slave address for a Write operation. If the EEPROM is still busy with the Write operation, no ACK
will be returned. If the GT24C02 has completed the Write operation, an ACK will be returned and the host
can then proceed with the next Read or Write operation.
READ OPERATION
Read operations are initiated in the same manner as Write operations, except that the (R/W) bit of the Slave
address is set to “1”. There are three Read operation options: current address read, random address read and
sequential read.
Current Address Read
The GT24C02 contains an internal address counter which maintains the address of the last byte accessed,
incremented by one. For example, if the previous operation is either a Read or Write operation addressed to
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