IS24C02B-2ZLI-TR ISSI, Integrated Silicon Solution Inc, IS24C02B-2ZLI-TR Datasheet - Page 10

• Manufacturer Part Number: IS24C02B-2ZLI-TR
• Description: IC EEPROM 2KBIT 1MHZ 8TSSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS24C02B-2ZLI-TR

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 400kHz, 1MHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Density: 2Kb
• Interface Type: Serial (2-Wire)
• Organization: 256x8
• Access Time (max): 400ns
• Frequency (max): 1MHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Supply Current: 3mA
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

GT24C02
the address location n, the internal address counter would increment to address location n+1. When the
EEPROM receives the Slave Addressing Byte with a Read operation (R/W bit set to “1”), it will respond an
ACK and transmit the 8-bit data byte stored at address location n+1. The Master should not acknowledge
the transfer but should generate a Stop condition so the GT24C02 discontinues transmission. If 'n' is the last
byte of the memory, the data from location '0' will be transmitted. (Refer to Figure 8. Current Address Read
Diagram.)
Random Address Read
Selective Read operations allow the Master device to select at random any memory location for a Read
operation. The Master device first performs a 'dummy' Write operation by sending the Start condition, Slave
address and byte address of the location it wishes to read. After the GT24C02 acknowledges the byte
address, the Master device resends the Start condition and the Slave address, this time with the R/W bit set
to one. The EEPROM then responds with its ACK and sends the data requested. The Master device does
not send an ACK but will generate a Stop condition. (Refer to Figure 9. Random Address Read Diagram.)
Sequential Read
Sequential Reads can be initiated as either a Current Address Read or Random Address Read. After the
GT24C02 sends the initial byte sequence, the Master device now responds with an ACK indicating it
requires additional data from the GT24C02. The EEPROM continues to output data for each ACK received.
The Master device terminates the sequential Read operation by pulling SDA High (no ACK) indicating the
last data word to be read, followed by a Stop condition. The data output is sequential, with the data from
address n followed by the data from address n+1,n+2 ... etc. The address counter increments by one
automatically, allowing the entire memory contents to be serially read during sequential Read operation.
When the memory address boundary of the array is reached, the address counter “rolls over” to address 0,
and the device continues to output data. (Refer to Figure 10. Sequential Read Diagram).
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