IS24C02B-2ZLI-TR ISSI, Integrated Silicon Solution Inc, IS24C02B-2ZLI-TR Datasheet - Page 8

• Manufacturer Part Number: IS24C02B-2ZLI-TR
• Description: IC EEPROM 2KBIT 1MHZ 8TSSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS24C02B-2ZLI-TR

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 400kHz, 1MHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Density: 2Kb
• Interface Type: Serial (2-Wire)
• Organization: 256x8
• Access Time (max): 400ns
• Frequency (max): 1MHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Supply Current: 3mA
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

GT24C02
6 DEVICE OPERATION
The GT24C02 serial interface supports communications using industrial standard 2-wire bus protocol, such
2
as I
C.
2-WIRE BUS
The two-wire bus is defined as Serial Data (SDA), and Serial Clock (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and the receiving devices as receivers. The bus is
controlled by Master device that generates the SCL, controls the bus access, and generates the Start and
Stop conditions. The GT24C02 is the Slave device.
The Bus Protocol:
Data transfer may be initiated only when the bus is not busy.
During a data transfer, the SDA line must remain stable whenever the SCL line is high. Any changes in the
SDA line while the SCL line is high will be interpreted as a Start or Stop condition.
The state of the SDA line represents valid data after a Start condition. The SDA line must be stable for the
duration of the High period of the clock signal. The data on the SDA line may be changed during the Low
period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start
condition and terminated by a Stop condition.
Start Condition
The Start condition precedes all commands to the device and is defined as a High to Low transition of SDA
when SCL is High. The EEPROM monitors the SDA and SCL lines and will not respond until the Start
condition is met.
Stop Condition
The Stop condition is defined as a Low to High transition of SDA when SCL is High. All operations must
end with a Stop condition.
Acknowledge (ACK)
After a successful data transfer, each receiving device is required to generate an ACK. The Acknowledging
device pulls down the SDA line.
Reset
The GT24C02 contains a reset function in case the 2-wire bus transmission on is accidentally interrupted
(e.g. a power loss), or needs to be terminated mid-stream. The reset is initiated when the Master device
creates a Start condition. To do this, it may be necessary for the Master device to monitor the SDA line
while cycling the SCL up to nine times. (For each clock signal transition to High, the Master checks for a
High level on SDA.)
Standby Mode
While in standby mode, the power consumption is minimal. The GT24C02 enters into standby mode during
one of the following conditions: a) After Power-up, while no Opcode is sent; b) After the completion of an
operation and followed by the Stop signal, provided that the previous operation is not Write related; or c)
After the completion of any internal write operations.
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