AD9683-170EBZ Analog Devices, AD9683-170EBZ Datasheet - Page 38

• Manufacturer Part Number: AD9683-170EBZ
• Description: Data Conversion IC Development Tools
• Manufacturer: Analog Devices
• Type: ADCr
• Series: AD9683r

Specifications of AD9683-170EBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9683-170
• Interface Type: SPI
• Operating Supply Voltage: 1.8 V
• Description/function: Evaluation board with AD9683-170
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 135 mA
• For Use With: AD9683-170

AD9683
Reg
Addr
(Hex)
0x65
0x67
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x79
0x80
0x8B
0xA8
0xFF
MEMORY MAP REGISTER DESCRIPTIONS
For more information on functions controlled in Address 0x00
to Address 0x21 and Address 0xFF, with the exception of Address
0x08 and Address 0x14, see the
Interfacing to High Speed ADCs via SPI.
Reg Addr
Name
JESD204B BID
config
JESD204B LID
config
JESD204B
scrambler (SCR)
and lane (L)
configuration
JESD204B
parameter, F
JESD204B
parameter, K
JESD204B
parameter, M
JESD204B
parameters,
N/CS
JESD204B
parameters,
subclass/N’
JESD204B
parameter, S
JESD204B
parameters, HD
and CF
JESD204B
RESV1
JESD204B
RESV2
JESD204B
CHKSUM
JESD204B
output driver
control
JESD204B LMFC
offset
JESD204B
preemphasis
Device update
(global)
Bit 7
(MSB)
JESD204B
scrambling
(SCR):
0 =
disabled,
1 =
enabled
JESD204B
HD value;
read only
Number of control bits
00 = no control bits
10 = 2 control bits
01 = 1 control bit
(CS = 0),
(CS = 1),
AN-877
(CS = 2)
(CS):
set value of K per JESD204B specifications, but must also be a multiple of four octets
Bit 6
01 = Subclass 1 (default)
set value to 0x04 for preemphasis off, and set value to 0x14 for preemphasis on
JESD204B subclass:
00 = Subclass 0,
Application Note,
JESD204B preemphasis enable option (consult factory for more details);
JESD204B number of octets per frame (F); calculated value; read only
Bit 5
Reserved;
set to 1
JESD204B number of converters (M); 0 = 1 converter
JESD204B number of frames per multiframe (K);
JESD204B checksum value for the output lane
Bit 4
JESD204B Reserved Field 1
JESD204B Reserved Field 2
JESD204B control words per frame clock cycle per link (CF); read only
Local multiframe clock (LMFC) phase offset value; reset value for
Rev. 0 | Page 38 of 44
JESD204B samples per converter per frame cycle (S); read only
JESD204B number of lanes (L); 0 = one lane per link (L = 1)
LMFC phase counter when SYSREF± is asserted; used for
Bit 3
deterministic delay applications
PDWN Modes (Address 0x08)
Bits[7:6]—Reserved
Bit 5—External PDWN mode
This bit controls the function of the PDWN pin. When this bit is 0,
asserting the PDWN pin results in a full power-down of the device.
When this bit is 1, asserting the PDWN pin places the device in
standby.
JESD204B LID value
JESD204B N’ value; 0xF = N’ = 16
0xD = 14-bit converter (N = 14)
ADC converter resolution (N),
Bit 2
JESD204B BID value
Bit 1
Bit 0 (LSB)
JESD204B
driver
power-
down:
0 =
enabled,
1 = powered
down
Transfer
settings
Default
0x80
0x00
0x0D
0x2F
0x00
0x00
0x04
Data Sheet
Notes
Read only
Read only
Read only
Typically not
required