AD9683-170EBZ Analog Devices, AD9683-170EBZ Datasheet - Page 35

• Manufacturer Part Number: AD9683-170EBZ
• Description: Data Conversion IC Development Tools
• Manufacturer: Analog Devices
• Type: ADCr
• Series: AD9683r

Specifications of AD9683-170EBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9683-170
• Interface Type: SPI
• Operating Supply Voltage: 1.8 V
• Description/function: Evaluation board with AD9683-170
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 135 mA
• For Use With: AD9683-170

Data Sheet
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17. Memory Map Registers
Reg
Addr
(Hex)
0x00
0x01
0x02
0x08
0x09
0x0A
0x0B
0x0D
0x10
Reg Addr
Name
SPI port
configuration
Chip ID
Chip grade
PDWN modes
Global clock
PLL status
Clock divide
Test mode
Customer offset
Bit 7
(MSB)
0
Reserved
PLL locked
status
(user pattern 1, 2, 3, 4, 1,
(user pattern 1, 2, 3, 4,
User test mode cycle:
00 = repeat pattern
10 = single pattern
then all zeros)
2, 3, 4, 1, …);
Bit 6
LSB first
Bit 5
Soft reset
External
PDWN
mode:
0 =
PDWN is
full
power-
down,
1 =
PDWN
puts
device in
standby
Long
pseudo-
random
number
generator
reset:
0 = long
PRN
enabled,
1 = long
PRN held
in reset
01 = RF clock divide by 2,
10 = RF clock divide by 4,
0x0 = 0 input clock cycles delayed,
0x1 = 1 input clock cycles delayed,
0x2 = 2 input clock cycles delayed,
0x7 = 7 input clock cycles delayed
00 = Nyquist clock,
Clock divide phase relative to
Clock selection:
00 = 250 MSPS,
11 = 170 MSPS
Speed grade:
11 = clock off
Offset adjust in LSBs from +31 to −32 (twos complement format):
the encode clock:
AD9683
Bit 4
1
JESD204B
standby
mode
(when
external
PDWN is
used):
0 =
JESD204B
core is
unaffected,
1 =
JESD204B
core is
powered
down
except for
PLL
Short
pseudo-
random
number
generator
reset:
0 = short
PRN
enabled,
1 = short
PRN held in
reset
Rev. 0 | Page 35 of 44
…
8-bit chip ID is 0xC3
00 0000 = adjust output by 0 (default),
01 1111 = adjust output by +31,
01 1110 = adjust output by +30,
10 0001 = adjust output by −31,
10 0000 = adjust output by −32
00 0001 = adjust output by +1,
Bit 3
1
JESD204B power modes:
stopped, digital circuitry
10 = standby mode, PLL
mode, PLL off, serializer
on, serializer off, clocks
digital held in reset;
off, clocks stopped,
00 = normal mode
01 = power-down
1000 = user test mode (use with Address 0x0D,
held in reset
(power-up);
Data output test generation mode:
Bits[7:6] and user pattern 1, 2, 3, 4),
0100 = alternating checkerboard,
…
…
Bit 2
Soft reset
Reserved for chip die revision, currently 0x0
0110 = PN sequence short,
0000 = off (normal mode),
0011 = negative full scale,
0101 = PN sequence long,
0010 = positive full scale,
0111 = 1/0 word toggle,
1001 to 1110 = unused,
0001 = midscale short,
1111 = ramp output
Clock divider ratio relative to
0x00 = divide by 1,
0x01 = divide by 2,
0x02 = divide by 3,
0x07 = divide by 8
the encode clock:
LSB first
Bit 1
does not affect JESD204B
01 = power-down mode,
10 = standby mode,
ADC power modes:
00 = normal mode
…
digital circuitry
(power-up),
Bit 0 (LSB)
0
Clock duty
cycle
stabilizer
enable
JESD204B
link is ready
0x00
0x00
Default
0x18
0xC3
0x00
or
0x30
0x00
0x01
0x00
AD9683
Notes
Read only
DCS enabled
if clock divider
enabled
Read only
Clock divide
values other
than 0x00
automatically
cause the DCS
to become
active