AD9683-170EBZ Analog Devices, AD9683-170EBZ Datasheet - Page 27

• Manufacturer Part Number: AD9683-170EBZ
• Description: Data Conversion IC Development Tools
• Manufacturer: Analog Devices
• Type: ADCr
• Series: AD9683r

Specifications of AD9683-170EBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9683-170
• Interface Type: SPI
• Operating Supply Voltage: 1.8 V
• Description/function: Evaluation board with AD9683-170
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 135 mA
• For Use With: AD9683-170

Data Sheet
Reenable Lane After Configuration
After modifying the JESD204B link parameters, enable the link so
that the synchronization process can begin. This is accomplished
by writing Logic 0 to Address 0x5F, Bit 0.
Table 13. JESD204B Typical Configurations
JESD204B
Configure
Setting
0x11 (Default)
Table 14. JESD204B Frame Alignment Monitoring and Correction Replacement Characters
Scrambling
Off
Off
Off
On
On
On
VIN+
VIN–
ADC
Lane Synchronization
On
On
Off
On
On
Off
A10
A11
A12
A13
CONVERTER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
M (No. of Converters),
Address 0x71,
Bits[7:0]
1
SYNCINB±
SYSREF±
TEST PATTERN
INPUT
16-BIT
ADC
FROM
DATA
ADC
CONVERTER
A10
A11
A12
A13
A8
A9
C0
C1
TEST PATTERN
A0
A1
A2
A3
A4
A5
A6
A7
JESD204B
8-BIT
L (No. of Lanes),
1
Character to be Replaced
Last octet in frame repeated from previous frame
Last octet in frame repeated from previous frame
Last octet in frame repeated from previous frame
Last octet in frame equals D28.7
Last octet in frame equals D28.3
Last octet in frame equals D28.7
Address 0x6E,
Bits[4:0]
(ADD TAIL BITS)
CONVERTER
ASSEMBLER
SAMPLE
Figure 59. Transmit Link Simplified Block Diagram
FRAME
Figure 60. Digital Processing of JESD204B Lane
SCRAMBLER
1 + x
OPTIONAL
Figure 61. ADC Output Data Path
14
+ x
15
Rev. 0 | Page 27 of 44
F (Octets/Frame),
Address 0x6F,
Bits[7:0], Read Only
2
S10
S11
S12
S13
S14
S15
S8
S9
SCRAMBLER
1 + x
OPTIONAL
S0
S1
S2
S3
S4
S5
S6
S7
14
REPLACEMENT
+ x
CHARACTER
ENCODER/
15
8B/10B
JESD204B LANE CONTROL
TEST PATTERN
(M = 1, L = 1)
JESD204B
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
S (Samples/ADC/Frame),
Address 0x74, Bits[4:0],
Read Only
1
ENCODER
10-BIT
8B/10B
AD9683 ADC
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
Last Octet in
Multiframe
No
Yes
Not applicable
No
Yes
Not applicable
SYNC
SERIALIZER
SYSREF±
TO
RECEIVER
t
E0 E1 E2 E3 E4 E5 E6 E7 E8 E9
SERDOUT0±
SERDOUT0±
Replacement Character
K28.7
K28.3
K28.7
K28.7
K28.3
K28.7
HD (High Density Mode),
Address 0x75, Bit 7,
Read Only
0
AD9683
. . .
E19