EVAL-AD7671EDZ Analog Devices, EVAL-AD7671EDZ Datasheet - Page 6

• Manufacturer Part Number: EVAL-AD7671EDZ
• Description: Data Conversion IC Development Tools EVALUATION BOARD
• Manufacturer: Analog Devices
• Type: ADCr
• Series: AD7671r

Specifications of EVAL-AD7671EDZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD7671
• Interface Type: SPI
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 1

AD7671
Pin
No.
1
2
3, 44–48
4
5
6
7
8
9, 10
11, 12
13
14
15
16
17
18
19
20
Mnemonic
AGND
AVDD
NC
BYTESWAP
OB/2C
WARP
IMPULSE
SER/PAR
D[2:3] or
DIVSCLK[0:1]
D[4]
or EXT/INT
D[5]
or INVSYNC
D[6]
or INVSCLK
D[7]
or RDC/SDIN
OGND
OVDD
DVDD
DGND
D[0:1]
Type
P
P
DI
DI
DI
DI
DO
DI/O
DI/O
DI/O
DI/O
DI/O
P
P
P
P
Analog Power Ground Pin.
Input Analog Power Pin. Nominally 5 V.
Parallel Mode Selection (8-/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB is
Mode Selection. When HIGH and WARP LOW, this input selects a reduced Power Mode.
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are
When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data
When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.
HIGH, output data is synchronized to an external clock signal connected to the SCLK input and
the external clock is gated by CS.
When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.
When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.
Input/Output Interface Digital Power Ground.
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host
Digital Power. Nominally at 5 V.
Description
No Connect.
output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight
binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal
shift register.
Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the maximum
throughput is achievable and a minimum conversion rate must be applied in order to guarantee
full specified accuracy. When LOW, full accuracy is maintained independent of the minimum
conversion rate.
In this mode, the power dissipation is approximately proportional to the sampling rate.
Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the Serial
Interface Mode is selected and some bits of the data bus are used as a Serial Port.
in high impedance.
Output Bus.
When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the Serial Master
Read after Convert Mode. These inputs, part of the Serial Port, are used to slow down, if desired,
the internal serial clock that clocks the data output. In the other serial modes, these pins are high
impedance outputs.
When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital select input for
choosing the internal or an external data clock, called Master and Slave Modes, respectively. With
EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic
When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state of
the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal. It is
active in both Master and Slave Mode.
When SER/PAR is HIGH, this input, part of the Serial Port, is used as either an external data input
or a read mode selection input, depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion
results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output
on DATA with a delay of 16 SCLK periods after the initiation of the read sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the Read Mode. When RDC/SDIN is HIGH,
the previous data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can
be output on SDOUT only when the conversion is complete.
interface (5 V or 3 V).
Digital Power Ground.
PIN FUNCTION DESCRIPTION
–6–
REV. C