TWR-K21D50M Freescale Semiconductor, TWR-K21D50M Datasheet - Page 8

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TWR-K21D50M

Manufacturer Part Number
TWR-K21D50M
Description
Development Boards & Kits - ARM
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of TWR-K21D50M

Rohs
yes
Product
Development Boards
Tool Is For Evaluation Of
MK21DN512VMC5
Core
ARM Cortex M4
Interface Type
USB
Operating Supply Voltage
1.8 V/3.3 V
Description/function
TWR-K21D50M MCU module is designed to work either in stand-alone mode or as part of the Freescale Tower System
For Use With
Freescale Tower Systems
6.2 Microcontroller
The TWR-K21D50M features the K21DN512VMB5 MCU. This 50 MHz microcontroller is part of the Kinetis K2x family
and is implemented in a 121 MAPBGA package. The following table notes some of the features of the
K21DN512VMB5 MCU.
Feature
Mixed-signal capability
Ultra low power
Flash and SRAM
Performance
Description
TWR-K21D50M Tower Module User’s Manual
11 low-power modes with power and clock gating for optimal
peripheral activity and recovery times.
Full memory and analog operation down to 1.71 V for extended battery
life
Low-leakage wake-up unit with up to six internal modules and sixteen
pins as wake-up sources in low-leakage stop (LLS) and very low-leakage
stop (VLLS) modes
Low-power timer for continual system operation in reduced power
states
512-KB flash featuring fast access times, high reliability, and four levels
of security protection
64 KB of SRAM
No user or system intervention to complete programming and erase
functions, and full operation down to 1.71 V
High-speed 16-bit ADC with configurable resolution
Single or differential output modes for improved noise rejection
500-ns conversion time achievable with programmable delay block
triggering
Two high-speed comparators providing fast and accurate motor over-
current protection by driving PWMs to a safe state
Optional analog voltage reference provides an accurate reference to
analog blocks and replaces external voltage references to reduce
system cost
50-MHz ARM Cortex-M4 core with DSP instruction set, single cycle
MAC, and single instruction multiple data (SIMD) extensions
Up to four channel DMA for peripheral and memory servicing with
reduced CPU loading and faster system throughput
Crossbar switch enables concurrent multi-master bus accesses,
increasing bus bandwidth
Independent flash banks allow concurrent code execution and firmware
updating with no performance degradation or complex coding routines
Table 1. Features of MK21DN512VMB5
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