MA240029 Microchip Technology, MA240029 Datasheet - Page 90

• Manufacturer Part Number: MA240029
• Description: Daughter Cards & OEM Boards PIC24FJ128GA310 Gen Purpose PIM
• Manufacturer: Microchip Technology

Specifications of MA240029

• Rohs: yes
• Product: Daughter Cards
• Core: PIC
• Description/function: Plug-in module
• Interface Type: I2C, SPI
• Tool Is For Evaluation Of: PIC24FJ128GA310
• For Use With: Explorer 16 Development Board

PIC24FJ128GA310 FAMILY
REGISTER 7-1:
DS39996F-page 90
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-10
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
Note 1:
TRAPR
EXTR
R/W-0
R/W-0
2:
3:
4:
(1)
(1)
All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the LPCFG Configuration bit is 1’ (unprogrammed), the retention regulator is disabled and the RETEN bit
has no effect.
Re-enabling the regulator after it enters Standby mode will add a delay, T
Sleep. Applications that do not use the voltage regulator should set this bit to prevent this delay from
occurring.
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or uninitialized W register is used as an
0 = An illegal opcode or uninitialized W Reset has not occurred
Unimplemented: Read as ‘0’
RETEN: Retention Mode Enable bit
1 = Retention mode is enabled while device is in Sleep modes (1.2V regulator supplies to the core)
0 = Retention mode is disabled; normal voltage levels are present
Unimplemented: Read as ‘0’
DPSLP: Deep Sleep Flag bit
1 = Device has been in Deep Sleep mode
0 = Device has not been in Deep Sleep mode
CM: Configuration Word Mismatch Reset Flag bit
1 = A Configuration Word Mismatch Reset has occurred
0 = A Configuration Word Mismatch Reset has not occurred
VREGS: Program Memory Power During Sleep bit
1 = Program memory bias voltage remains powered during Sleep
0 = Program memory bias voltage is powered down during Sleep
EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
SWR: Software Reset (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
IOPUWR
SWR
R/W-0
R/W-0
Address Pointer and caused a Reset
RCON: RESET CONTROL REGISTER
(1)
(1)
U = Unimplemented bit, read as ‘0’
W = Writable bit
‘1’ = Bit is set
SWDTEN
R/W-0
U-0
—
(4)
(1)
(1)
RETEN
WDTO
R/W-0
R/W-0
(2)
(1)
(1)
(2)
(1)
HS = Hardware Settable bit
‘0’ = Bit is cleared
SLEEP
R/W-0
U-0
(1)
—
(3)
(1)
DPSLP
IDLE
R/W-0
R/W-0
(1)
 2010-2011 Microchip Technology Inc.
(1)
(1)
VREG
x = Bit is unknown
, when waking up from
BOR
R/W-0
R/W-1
CM
(1)
(1)
VREGS
POR
R/W-0
R/W-1
(1)
bit 8
bit 0
(3)