ADP1046DC1-EVALZ Analog Devices, ADP1046DC1-EVALZ Datasheet - Page 73

• Manufacturer Part Number: ADP1046DC1-EVALZ
• Description: Daughter Cards & OEM Boards ADP1046 Daughter Card
• Manufacturer: Analog Devices
• Series: ADP1046r

Specifications of ADP1046DC1-EVALZ

• Rohs: yes
• Product: Daughter Cards
• Description/function: 100 kHz daughter board
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.3 V
• Factory Pack Quantity: 1
• For Use With: ADP1046

Data Sheet
Table 86. Register 0x56—SR2 Rising Edge Setting (SR2 Pin)
Bits
[7:4]
3
2
[1:0]
Table 87. Register 0x57—SR2 Falling Edge Timing (SR2 Pin)
Bits
[7:0]
Table 88. Register 0x58—SR2 Falling Edge Setting (SR2 Pin)
Bits
[7:4]
3
2
[1:0]
Table 89. Register 0x59—OUTAUX Rising Edge Timing (OUTAUX Pin)
Bits
[7:0]
Bit Name
t
Modulate enable
t
Reserved
Bit Name
t
Bit Name
t
Modulate enable
t
Reserved
Bit Name
t
11
11
12
12
12
13
sign
sign
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
These bits contain the four LSBs of the 12-bit t
bits of Register 0x55, which contains the eight MSBs of the t
resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and t_fall of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise and t_fall
occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
between 80 ns and 115 ns when using the SR soft start.
1 = PWM modulation acts on the t
0 = no PWM modulation of the t
1 = negative sign. Increase of PWM modulation moves t
0 = positive sign. Increase of PWM modulation moves t
Reserved.
Description
This register contains the eight MSBs of the 12-bit t
four bits of Register 0x58, which contains the four LSBs of the t
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and t_fall
of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise and
t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. The
absolute maximum pulse width is t
Description
These bits contain the four LSBs of the 12-bit t
bits of Register 0x57, which contains the eight MSBs of the t
resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and t_fall of a
PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise and t_fall
occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
1 = PWM modulation acts on the t
0 = no PWM modulation of the t
1 = negative sign. Increase of PWM modulation moves t
0 = positive sign. Increase of PWM modulation moves t
Reserved.
Description
This register contains the eight MSBs of the 12-bit t
four bits of Register 0x5A, which contains the four LSBs of the t
5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and t_fall of
a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise and t_fall
occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute
maximum pulse width is t
frequency, there is a constant lag/lead time between this edge and the other edges (t
fore, OUTAUX is not synchronized to the other PWM outputs but can be made synchronous by
adjusting the delay accordingly. If either the OUTAUX switching frequency (Register 0x3F) or the
PWM switching frequency (Register 0x40) is changed after edge adjustment, the synchronization
between OUTAUX and the PWM edges is no longer maintained. The OUTAUX delay must be adjusted
again to synchronize the edges to the PWM edges for the new set of switching frequencies.
Rev. B | Page 73 of 92
PERIOD
PERIOD
PERIOD
− 5 ns. It is recommended that the SR2 rising edge not be set
− 5 ns.
− 5 ns. Depending on the switching frequency and the OUTAUX
11
12
11
edge.
12
edge.
PERIOD
edge.
edge.
− 5 ns.
11
12
time. This value is always used with the eight
time. This value is always used with the eight
12
13
time. This value is always used with the top
time. This value is always used with the top
11
12
11
12
left.
left.
right.
right.
11
12
time. Each LSB corresponds to 5 ns
time. Each LSB corresponds to 5 ns
12
13
time. Each LSB corresponds to
time. Each LSB corresponds to
ADP1046
1
to t
12
); there-