EVAL-AD5110SDZ Analog Devices, EVAL-AD5110SDZ Datasheet - Page 9

• Manufacturer Part Number: EVAL-AD5110SDZ
• Description: Digital Potentiometer Development Tools Evaluation board
• Manufacturer: Analog Devices
• Series: AD5110r

Specifications of EVAL-AD5110SDZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD5110
• Resistance: 10 kOhms
• Operating Supply Voltage: 5.5 V
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Factory Pack Quantity: 1

Data Sheet
INTERFACE TIMING SPECIFICATIONS
V
Table 5.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
SCL
1
2
3
4
5
6
7
8
9
10
11
11A
12
SP
EEPROM_PROGRAM
POWER_UP
RESET
Maximum bus capacitance is limited to 400 pF.
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode.
EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles.
Maximum time after V
LOGIC
3
2
= 1.8 V to 5.5 V; all specifications T
5
1
4
Test Conditions/
Comments
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Fast mode
DD
is equal to 2.3 V.
Min
4.0
0.6
4.7
1.3
250
100
0
0
4.7
0.6
4
0.6
4.7
1.3
4
0.6
20 + 0.1 C
20 + 0.1 C
20 + 0.1 C
20 + 0.1 C
20 + 0.1 C
0
MIN
to T
L
L
L
L
L
MAX
, unless otherwise noted.
Typ
15
Rev. B | Page 9 of 28
Max
100
400
3.45
0.9
1000
300
300
300
1000
300
1000
300
300
300
50
50
50
25
Unit
kHz
kHz
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
µs
Description
Serial clock frequency
t
t
t
t
t
t
t
condition
t
t
t
t
t
condition and after an acknowledge bit.
t
Pulse width of suppressed spike
Memory program time
Power-on EEPROM restore time
Reset EEPROM restore time
HIGH
LOW
SU;DAT
HD;DAT
SU;STA
HD;STA
BUF
SU;STO
RDA
FDA
RCL
RCL1
FCL
, rise time of SCL signal
, fall time of SCL signal
, bus free time between a stop and a start
, fall time of SDA signal
, rise time of SDA signal
, SCL low time
, rise time of SCL signal after a repeated start
, SCL high time
, setup time for a repeated start condition
, data setup time
, hold time (repeated) start condition
, setup time for stop condition
, data hold time
AD5110/AD5112/AD5114