Si53154-EVB Silicon Labs, Si53154-EVB Datasheet

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Si53154-EVB

Manufacturer Part Number
Si53154-EVB
Description
Clock & Timer Development Tools 4 PCIe BUFFER
Manufacturer
Silicon Labs
Type
Clock Buffersr
Datasheet

Specifications of Si53154-EVB

Rohs
yes
Product
Evaluation Boards
Tool Is For Evaluation Of
Si53154
Frequency
100 MHz to 210 MHz
Operating Supply Voltage
3.3 V
Interface Type
I2C, PCIe
Si53154 E
Description
The Si53154 is a four port PCIe clock buffer compliant
to the PCIe Gen1, Gen2 and Gen3 standards. The
Si53154 is a 24-pin QFN device that operates on a
3.3 V power supply and can be controlled using SMBus
signals along with hardware control input pins. The
device is spread aware and accepts a frequency spread
differential clock frequency range from 100 to 210 MHz.
The connections are described in this document.
Rev. 0.1 1/12
VALUATION
DIFF3 Output Enable
DIFF1 Output Enable
DIFF2 Output Enable
DIFF0 Output Enable
GND
Copyright © 2012 by Silicon Labs
B
OARD
EVB Features
This document is intended to be used in conjunction
with the Si53154 device and data sheet for the following
tests:
power supply
connection for
VDD = 3.3V
SDATA
SCLK
application
Power connectors
PCIe Gen1, Gen2, Gen3 compliancy
Power consumption test
Jitter performance
Testing out I
In-system validation where SMA connectors are
present
SRC0
U
SER
Si53154
Si 53154- E VB
2
connection for
S
C code for signal tuning
application
SRC1
Clock Input
Differential
G
UIDE
Si53154-EVB
connection
application
connection
application
SRC3
SRC2
for
for

Related parts for Si53154-EVB

Si53154-EVB Summary of contents

Page 1

... In-system validation where SMA connectors are present VDD = 3.3V GND power supply Power connectors SDATA SCLK Si53154 SRC0 connection for connection for application application Copyright © 2012 by Silicon Labs G UIDE Differential Clock Input SRC3 connection for application SRC2 connection for application SRC1 Si53154-EVB ...

Page 2

... Si53154-EVB 1. Front Panel Differential Buffer Input for on Si53154-EVB only 3.3V Power Supply Connector GND Connector VDD Connectors OE1 hardware input control for DIFF1 output No Connect OE2 hardware input control for DIFF2 output OE0 hardware input control for DIFF0 output Si53154 device mount Figure 1 ...

Page 3

... C control bits and hardware pins are listed in Table Control Bit Byte1 [bit 2] Byte1 [bit 0] Byte2 [bit 7] Byte2 [bit control bit in Control register. The hardware pin and the Table 2. Output Enable Control Output DIFF0 DIFF1 DIFF2 DIFF3 Rev. 0.1 Si53154-EVB Hardware Control Input OE0 OE1 OE2 OE3 3 ...

Page 4

... Si53154-EVB 2. Schematics For Si52144,R10 open For Si53154,R11 open VDD1 R10 0 R11 NI SSON VDD1 VDD6 VDD12 VDD17 VDD21 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF DUTGND VCC_3.3V JP1 JP2 JP3 JUMPER JUMPER JUMPER C13 + C9 + C10 C17 C14 1uF 1uF 1uF ...

Page 5

... SHORT AS POSSIBLE SMA DUTGND DIFF1_1 SMA C32 DIFF3 2.0pF DUTGND C34 DIFF3# 2.0pF DIFF1#_1 L1 SHOULD BE SHORT AS POSSIBLE SMA Figure 5. Differential Clock Signals Rev. 0.1 Si53154-EVB SCLK/SDATA VDD_3.3V XIN_DIFFIN#1 SMA R15 10K SCLK DUTGND VDD_3.3V XOUT_DIFFIN1 DUTGND SMA R17 10K SDATA DUTGND DIFF2_1 ...

Page 6

... Si53154-EVB C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...

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