AT25DF021-SSHF-B Atmel, AT25DF021-SSHF-B Datasheet - Page 8

• Manufacturer Part Number: AT25DF021-SSHF-B
• Description: IC FLASH 2MBIT 70MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT25DF021-SSHF-B

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 2M (256K x 8)
• Speed: 70MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Memory Configuration: 1024 Pages X 256 Bytes
• Interface Type: Serial, SPI
• Clock Frequency: 66MHz
• Supply Voltage Range: 2.3V To 3.6V
• Memory Case Style: SOIC
• Rohs Compliant: Yes
• Data Bus Width: 8 bit
• Architecture: Sectored
• Timing Type: Synchronous
• Access Time: 6 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 16 mA
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7. Read Commands
7.1
Figure 7-1.
Figure 7-2.
8
Read Array
SCK
AT25DF021
SO
CS
SI
Read Array - 0Bh Opcode
Read Array - 03h Opcode
SCK
SO
CS
SI
HIGH-IMPEDANCE
MSB
0
0
0
1
The Read Array command can be used to sequentially read a continuous stream of data from
the device by simply providing the clock signal once the initial starting address has been speci-
fied. The device incorporates an internal address counter that automatically increments on every
clock cycle.
Two opcodes (0Bh and 03h) can be used for the Read Array command. The use of each
opcode depends on the maximum clock frequency that will be used to read data from the
device. The 0Bh opcode can be used at any clock frequency up to the maximum specified by
f
specified by f
To perform the Read Array operation, the CS pin must first be asserted and the appropriate
opcode (0Bh or 03h) must be clocked into the device. After the opcode has been clocked in, the
three address bytes must be clocked in to specify the starting address location of the first byte to
read within the memory array. Following the three address bytes, an additional dummy byte
needs to be clocked into the device if the 0Bh opcode is used for the Read Array operation.
After the three address bytes (and the dummy byte if using opcode 0Bh) have been clocked in,
additional clock cycles will result in data being output on the SO pin. The data is always output
with the MSB of a byte first. When the last byte (03FFFFh) of the memory array has been read,
the device will continue reading back at the beginning of the array (000000h). No delays will be
incurred when wrapping around from the end of the array to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-
ance state. The CS pin can be deasserted at any time and does not require that a full byte of
data be read.
CLK
0
2
OPCODE
, and the 03h opcode can be used for lower frequency read operations up to the maximum
0
3
MSB
HIGH-IMPEDANCE
1
0
4
0
0
0
5
1
1
0
6
2
OPCODE
RDLF
1
0
7
3
MSB
A
0
8
4
.
A
0
9
5
ADDRESS BITS A23-A0
A
1
10 11
6
A
1
7
MSB
A
A
12
8
A
A
9
ADDRESS BITS A23-A0
A
10 11
A
A
29 30
A
12
A
A
A
31 32
MSB
X
X
A
33
29 30
DON'T CARE
X
A
34
X
A
35
31 32
MSB
X
D
36
X
D
33
37 38
DATA BYTE 1
X
D
34
X
D
39
35
MSB
D
D
40
36
D
D
41
37 38
DATA BYTE 1
D
D
42 43
D
D
39 40
MSB
D
D
44
D
D
45
D
46
D
47 48
MSB
D
3677D–DFLASH–04/09
D