AT25DF021-SSHF-B Atmel, AT25DF021-SSHF-B Datasheet - Page 13

• Manufacturer Part Number: AT25DF021-SSHF-B
• Description: IC FLASH 2MBIT 70MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT25DF021-SSHF-B

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 2M (256K x 8)
• Speed: 70MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Memory Configuration: 1024 Pages X 256 Bytes
• Interface Type: Serial, SPI
• Clock Frequency: 66MHz
• Supply Voltage Range: 2.3V To 3.6V
• Memory Case Style: SOIC
• Rohs Compliant: Yes
• Data Bus Width: 8 bit
• Architecture: Sectored
• Timing Type: Synchronous
• Access Time: 6 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 16 mA
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.2
9.3
3677D–DFLASH–04/09
Write Disable
Protect Sector
The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Reg-
ister to the logical “0” state. With the WEL bit reset, all Byte/Page Program, erase, Protect
Sector, Unprotect Sector, Program OTP Security Register, and Write Status Register com-
mands will not be executed. Other conditions can also cause the WEL bit to be reset; for more
details, refer to the WEL bit section of the Status Register description.
To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h
must be clocked into the device. No address bytes need to be clocked into the device, and any
data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in
the Status Register will be reset to a logical “0”. The complete opcode must be clocked into the
device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte
boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of
the WEL bit will not change.
Figure 9-2.
Every physical 64-Kbyte sector of the device has a corresponding single-bit Sector Protection
Register that is used to control the software protection of a sector. Upon device power-up, each
Sector Protection Register will default to the logical “1” state indicating that all sectors are pro-
tected and cannot be programmed or erased.
Issuing the Protect Sector command to a particular sector address will set the corresponding
Sector Protection Register to the logical “1” state. The following table outlines the two states of
the Sector Protection Registers.
Table 9-1.
Before the Protect Sector command can be issued, the Write Enable command must have been
previously issued to set the WEL bit in the Status Register to a logical “1”. To issue the Protect
Sector command, the CS pin must first be asserted and the opcode of 36h must be clocked into
the device followed by three address bytes designating any address within the sector to be pro-
tected. Any additional data clocked into the device will be ignored. When the CS pin is
deasserted, the Sector Protection Register corresponding to the physical sector addressed by
A23-A0 will be set to the logical “1” state, and the sector itself will then be protected from
Value
0
1
Sector Protection Status
Sector is unprotected and can be programmed and erased.
Sector is protected and cannot be programmed or erased. This is the default state.
Write Disable
Sector Protection Register Values
SCK
SO
CS
SI
HIGH-IMPEDANCE
MSB
0
0
0
1
0
2
OPCODE
0
3
0
4
1
5
0
6
0
7
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