AT88SC153-10SU-00 Atmel, AT88SC153-10SU-00 Datasheet - Page 8

• Manufacturer Part Number: AT88SC153-10SU-00
• Description: IC EEPROM 2KBIT 1MHZ 8SOIC
• Manufacturer: Atmel
• Series: CryptoMemory®r

Specifications of AT88SC153-10SU-00

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 1MHz
• Interface: Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.13
8
Checksum Authentication Register
AT88SC153
Table 6-2.
Programmable Chip Select (CS0–CS3): The four most significant bits (b4–b7) of every com-
mand comprise the chip select address. All AT88SC153 devices will respond to the default chip
select address of $B (1011). Each device will also respond to a second chip select address pro-
grammed into CS0–CS3 of the device configuration register. By programming each device to a
unique chip select address, it is possible to connect up to 15 devices on the same serial data
bus. The Write EEPROM and Verify Password commands can be used globally to all devices
sharing the bus by using the default chip select address $B.
Eight Trials Allowed (ETA): If enabled (ETA = “0”), the ETA extends the trials limit to eight
incorrect presentations allowed (passwords or authentication). If disabled (ETA = “1”), the PAC
and AAC will allow only four incorrect attempts.
Unlimited Authentication Trials (UAT): If enabled (UAT = “0”), the AAC is disabled, allowing
an unlimited number of authentication attempts. The PACs are not affected by the UAT bit.
Unlimited Checksum Reads (UCR): If enabled (UCR = “0”), the device will allow an unlimited
number of checksums without requiring a new authentication.
Supervisor Mode Enable (SME): If enabled (SME = “0”), verification of the Write 1 password
will allow the user to write and read the entire passwords zone (including the PACs).
After a valid authentication has been completed, the internal pseudo-random generator (PRG)
will compute a secure checksum after one write command or several consecutive write com-
mands. This checksum certifies that the data sent by the host during the write commands were
received and therefore written in the memory. For every write command, the device clocks the
data bytes into the PRG and its output is the Checksum Authentication Register (CAR), which is
a function of Ci, Gc, Q, and the data bytes written.
After a valid authentication, any write command will enable the checksum mode and cause AAC
to become the virtual location of the 8-byte CAR. When all data have been transmitted, the host
may perform a Read CAR command by sending a read command with the AAC address ($20).
The first 8 bytes transmitted by the device form the secure checksum.
The checksum mode allows only a single Read CAR operation for each valid authentication. The
checksum mode is disabled at the end of the Read CAR command, whatever the number of
bytes transmitted, or by a read command with any other address. The checksum mode can only
be enabled once for a given authentication.
Note: During the Read CAR command, the internal address counter is incremented just as in a
normal read command. Once 8 bytes have been transmitted, the checksum mode is automati-
cally disabled, and if the host continues to request data, the device responds as to a normal read
command, from the address $28.
Bit 7
SME
Bit 6
UCR
Device Configuration Options
Bit 5
UAT
Bit 4
ETA
Bit 3
CS3
Bit 2
CS2
Bit 1
CS1
Bit 0
CS0
1016E–SMEM–12/07