ZLF645S0Q2032G Maxim Integrated, ZLF645S0Q2032G Datasheet - Page 85

• Manufacturer Part Number: ZLF645S0Q2032G
• Description: 8-bit Microcontrollers - MCU Crimzon Flash Infrared MCU
• Manufacturer: Maxim Integrated

Specifications of ZLF645S0Q2032G

• Core: Z8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 1 KB
• On-chip Adc: No
• Operating Supply Voltage: 2 V to 3.6 V
• Package / Case: QFN-EP-20
• Mounting Style: SMD/SMT
• Interface Type: UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 8 bit, 1 x 16 bit
• On-chip Dac: No
• Processor Series: ZLF645
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2 V

Table 34. Flash Status Register (FSTAT)
19-4572; Rev 0; 4/09
Bits
Field
Reset
R/W
Address
Bit Position
[7:6]
[5:0]
Flash Status Register
Flash Page Select Register
R
7
0
The Flash Status (FSTAT) register (see
Controller. This register can be read any time. The read-only Flash Status (FSTAT) 
register shares its Register File address with the Write-only Flash Control (FCTL) register.
The Flash Page Select (FPS) register (see
Sector Protect (FSEC) register. Unless the Flash Controller is in ‘locked’ state and its
Flash Control (FCTL) register is written with
Page Select (FPS) register.
The FPS register is used to select one page within the Flash Main Memory or Information
Block for programming or erasure depending upon whether its IFEN bit is 0 or 1 respec-
tively. Each Flash Main Memory Page contains 512 bytes of Flash memory. During a Page
Erase operation to the Main Memory, the page that will be erased is the one containing the
512 Flash memory locations where bits 15 through 9 of their addresses is equal to bits 6
through 0 of FPS register. For Main Memory programming operations, bits 15 through 9
of the address to be programmed must equal bits 6 through 0 of the FPS register for the
Flash Controller to execute the operation. For page erase or programming operations to
the Flash’s Information Block as indicated by the IFEN bit being 1, the programming or
Reserved
000000
000001
000010
000100
000011
001xxx
010xxx
100xxx
Value
—
R
6
0
Description
Reserved —Reads as 0’s.
FSTAT —Flash Controller Status
Flash Controller locked. 
First unlock command received (73H written). 
Second unlock command received (8CH written). 
Flash Controller unlocked.
Sector protect register selected.
Program operation in progress. 
Page erase operation in progress. 
Mass erase operation in progress.
R
5
0
Bank F, Register address: 01H
R
4
0
Table
Table
34) indicates the current state of the Flash
5EH
R
3
0
35) shares address space with the Flash
FSTAT
, writes to this address target the Flash
ZLF645 Series Flash MCUs
R
2
0
Flash Control Register Definitions
Product Specification
R
1
0
R
0
0
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