ZLF645S0Q2032G Maxim Integrated, ZLF645S0Q2032G Datasheet - Page 150

• Manufacturer Part Number: ZLF645S0Q2032G
• Description: 8-bit Microcontrollers - MCU Crimzon Flash Infrared MCU
• Manufacturer: Maxim Integrated

Specifications of ZLF645S0Q2032G

• Core: Z8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 1 KB
• On-chip Adc: No
• Operating Supply Voltage: 2 V to 3.6 V
• Package / Case: QFN-EP-20
• Mounting Style: SMD/SMT
• Interface Type: UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 8 bit, 1 x 16 bit
• On-chip Dac: No
• Processor Series: ZLF645
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2 V

Table 68. Watchdog Timer Mode Register (WDTMR)
19-4572; Rev 0; 4/09
Bit
Field
Reset
R/W
Address
Bit Position
[7]
[3] 
[2]
[6:4], [1:0]
Note:
Note:
Using the Watchdog Timer As a Stop Mode Recovery Source
—
W
001_XX
010_XX
100_XX
7
0
000_00
000_01
000_10
000_11
WDTMR register cannot be read. The register is located in Bank F of the Expanded Reg-
ister Group at address location
This register is not reset after a Stop Mode Recovery.
Although not explicitly shown above, if any two bits of bits 6 through 4 are programmed to
1 or if all three bits are programmed to 0, then the time-out period depends on bits 1 and 0
only as shown for the [6:4]=000 case.
As mentioned previously, timeout of the Watchdog Timer generates a chip reset that
removes the ZLF645 from STOP mode. This feature is used to configure the ZLF645 to
automatically exit STOP mode, once it is in STOP mode. This is done within a set maxi-
mum period of time based upon the Watchdog Timer timeout setting. In this way, the
Value
—
0
1
0
1
W
6
0
Time-Out Select
Description
Reserved —Reads are undefined; must write 0000.
WDT During STOP Mode —Determines if WDT is active during STOP mode.
Off.
WDT active during STOP mode.
WDT During HALT Mode —Determines if WDT is active during HALT mode.
See
Off.
WDT active during HALT mode.
Time-Out Select —Selects the WDT time period (see Note below).
5 ms minimum
10 ms minimum
20 ms minimum
80 ms minimum
320 ms minimum
1, 280 ms minimum
5,120 ms minimum
Figure 43
W
5
0
W
4
0
on page 138.
WDT During STOP
Bank F: 0Fh; Linear: F0Fh
0Fh
Mode
.
W
3
1
WDT During HALT
Mode
W
2
1
ZLF645 Series Flash MCUs
Product Specification
Time-Out Select
W
1
0
Watchdog Timer
W
0
1
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