C8051F047R Silicon Labs, C8051F047R Datasheet - Page 159

• Manufacturer Part Number: C8051F047R
• Description: 8-bit Microcontrollers - MCU 25 MIPS 32KB 10ADC
• Manufacturer: Silicon Labs

Specifications of C8051F047R

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 4.25 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.7 V to 3.6 V
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 13
• Data Rom Size: 64 KB
• Interface Type: CAN, SMBus, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Processor Series: C8051
• Program Memory Type: Flash
• Factory Pack Quantity: 500
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V

Bit7:
Bit6:
Bit6:
Bit6:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
Bit7
Reserved. Read = 0b, Write = don’t care.
CP2IE: Enable Comparator (CP2) Interrupt.
This bit sets the masking of the CP2 interrupt.
0: Disable CP2 interrupts.
1: Enable interrupt requests generated by the CP2IF flag.
CP1IE: Enable Comparator (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by the CP1IF flag.
CP0IE: Enable Comparator (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0IF flag.
EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
EWADC0: Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison Interrupt.
1: Enable Interrupt requests generated by ADC0 Window Comparisons.
ESMB0: Enable System Management Bus (SMBus0) Interrupt.
This bit sets the masking of the SMBus interrupt.
0: Disable all SMBus interrupts.
1: Enable interrupt requests generated by the SI flag.
ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of SPI0 interrupt.
0: Disable all SPI0 interrupts.
1: Enable Interrupt requests generated by the SPI0 flag.
CP2IE
SFR Definition 12.13. EIE1: Extended Interrupt Enable 1
R/W
Bit6
CP1IE
R/W
Bit5
CP0IE
R/W
Bit4
Rev. 1.5
EPCA0
R/W
Bit3
C8051F040/1/2/3/4/5/6/7
EWADC0
R/W
Bit2
ESMB0
R/W
Bit1
SFR Address:
ESPI0
SFR Page:
R/W
Bit0
0xE6
All Pages
00000000
Reset Value
159