ZLF645E0Q2032G Maxim Integrated, ZLF645E0Q2032G Datasheet - Page 82

• Manufacturer Part Number: ZLF645E0Q2032G
• Description: 8-bit Microcontrollers - MCU Crimzon Flash Infrared MCU
• Manufacturer: Maxim Integrated

Specifications of ZLF645E0Q2032G

• Core: Z8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 1 KB
• On-chip Adc: No
• Operating Supply Voltage: 2 V to 3.6 V
• Package / Case: QFN-EP-20
• Mounting Style: SMD/SMT
• Interface Type: UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 8 bit, 1 x 16 bit
• On-chip Dac: No
• Processor Series: ZLF645
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2 V

19-4572; Rev 0; 4/09
Byte Programming
Page Erase
settings of the Sector Protect (FSEC) register. After a bit of the Sector Protect register has
been set, it cannot be cleared except by powering down the device.
All Flash accesses either through CPU code execution or through the ICP interface occur
using the Flash memory byte mode of operation. The Flash Controller allows CPU
programming access to the Flash’s main memory area only whereas the ICP has access to
both the main memory and the page 3 information area for programming. The Flash
memory is enabled for byte programming by either the CPU or the ICP after unlocking the
Flash Controller and executing either a Mass Erase or Page Erase operation. When the
Flash Controller is unlocked and a main memory Mass Erase is executed, all Flash Main
Memory locations are available for byte programming by the CPU. In contrast, when the
Flash Controller is unlocked and a main memroy Page Erase is executed, only the
locations of the selected page as per the Page Select (PGS) register are available for byte
programming by the CPU. An erased Flash byte contains all 1’s (
The programming operation can only be used to change bits from 1 to 0. To change a
Flash bit (or multiple bits) from 0 to 1 requires an erase operation through execution of
either a Page Erase or Mass Erase command to the Flash Controller.
Byte Programming can be accomplished through the ICP by using the Write Memory
command or by the Z8 LXMC CPU through execution of the LDC or LDCI instructions.
For a description of the LDC and LDCI instructions, refer to Z8
Manual (UM0215). During execution of a CPU initiated programming operation the 
system clock to the CPU is halted preventing further code execution, however the system
clock and the on-chip peripherals continue to operate. Once the programming operation is
complete, the CPU resumes code execution. To exit programming mode and lock the
Flash the CPU can perform a write of any value to the Flash Control (FCTL) register,
except the Mass Erase or Page Erase commands.
The Flash main memory can be erased one page (512 bytes) at a time. Page Erasing the
Flash memory sets all bytes in that page to the value
register identifies the page to be erased. For CPU initiated page erase operations, only a
page residing in an unprotected sector can be erased. With the Flash Controller unlocked
and the active page set, writing the value
ates the Page Erase operation. As with programming, during execution of a CPU initiated
page erase operation the system clock to the CPU is halted preventing further code execu-
tion, however the system clock and the on-chip peripherals continue to operate. Once the
page erase operation is complete, the CPU resumes code execution.
If a Page Erase operation to the Flash’s main memory is performed using the ICP, bit 3 of
the ICP Status register can be polled to determine when the operation is complete. When
the Page Erase is complete, the Flash Controller returns to its locked state. Although the
95H
to the Flash Control (FCTL) register initi-
FFH
ZLF645 Series Flash MCUs
. The Flash Page Select (PGS)
®
Product Specification
FFH
LXMC CPU User
Flash Controller Overview
).

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