ZLF645E0Q2032G Maxim Integrated, ZLF645E0Q2032G Datasheet - Page 141

• Manufacturer Part Number: ZLF645E0Q2032G
• Description: 8-bit Microcontrollers - MCU Crimzon Flash Infrared MCU
• Manufacturer: Maxim Integrated

Specifications of ZLF645E0Q2032G

• Core: Z8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 1 KB
• On-chip Adc: No
• Operating Supply Voltage: 2 V to 3.6 V
• Package / Case: QFN-EP-20
• Mounting Style: SMD/SMT
• Interface Type: UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 8 bit, 1 x 16 bit
• On-chip Dac: No
• Processor Series: ZLF645
• Program Memory Type: Flash
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2 V

Table 65. Interrupt Mask Register (IMR)
19-4572; Rev 0; 4/09
Bit
Field
Reset
R/W
Address
Bit Position
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Interrupt Mask Register
Master Interrupt
Bits [5:0] are used to enable the interrupt. Bit 7 is the status of the master interrupt. When
reset, all interrupts are disabled. When writing 1 to bit 7, you must also execute the EI
instruction to enable interrupts (see
Value
Enable
R/W
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
7
0
Description
Master Interrupt Enable
Use only DI and EI instructions to alter this bit. Always disable interrupts (DI
instruction) before writing this register.
All interrupts are disabled.
Interrupts are enabled/disabled individually in bits [5:0].
Reserved
Reads are undefined; Must be written to 1.
Disables IRQ5.
Enables IRQ5.
Disables IRQ4.
Enables IRQ4.
Disables IRQ3.
Enables IRQ3.
Disables IRQ2.
Enables IRQ2.
Disables IRQ1.
Enables IRQ1.
Disables IRQ0.
Enables IRQ0.
Reserved
—
X
6
Bank Independent: FBh; Linear: 0FBh
Enable
IRQ5
R/W
X
5
Table
Enable
IRQ4
R/W
X
4
65).
Enable
IRQ3
R/W
X
3
ZLF645 Series Flash MCUs
Enable
IRQ2
R/W
X
2
Product Specification
Interrupt Mask Register
Enable
IRQ1
R/W
X
1
Enable
IRQ0
R/W
X
0
133