SST89E554RC-40-C-PI Microchip Technology, SST89E554RC-40-C-PI Datasheet - Page 65

• Manufacturer Part Number: SST89E554RC-40-C-PI
• Description: 8-bit Microcontrollers - MCU 32KB+8KB 40ns
• Manufacturer: Microchip Technology

Specifications of SST89E554RC-40-C-PI

• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 1 KB
• On-chip Adc: No
• Operating Supply Voltage: 4.5 V to 5.5 V
• Package / Case: PDIP-40
• Mounting Style: Through Hole
• Data Rom Size: 128 B
• Interface Type: SPI, UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• On-chip Dac: No
• Processor Series: FlashFlex
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

FlashFlex MCU
SST89E564RD / SST89V564RD
SST89E554RC / SST89V554RC
11.0 POWER-SAVING MODES
The device provides two power saving modes of operation
for applications where power consumption is critical. The
two modes are idle and power-down, see Table 11-1.
11.1 Idle Mode
Idle mode is entered setting the IDL bit in the PCON regis-
ter. In idle mode, the program counter (PC) is stopped. The
system clock continues to run and all interrupts and periph-
erals remain active. The on-chip RAM and the special func-
tion registers hold their data during this mode.
The device exits idle mode through either a system inter-
rupt or a hardware reset. Exiting idle mode via system
interrupt, the start of the interrupt clears the IDL bit and
exits idle mode. After exit the Interrupt Service Routine, the
interrupted program resumes execution beginning at the
instruction immediately following the instruction which
invoked the idle mode. A hardware reset starts the device
similar to a power-on reset.
TABLE 11-1: P
©2007 Silicon Storage Technology, Inc.
Power-down
Idle Mode
Mode
Mode
(Set IDL bit in PCON)
(Set PD bit in PCON)
MOV PCON, #01H;
MOV PCON, #02H;
OWER
Initiated by
Software
Software
S
AVING
M
ODES
CLK is running.
Interrupts, serial port and
timers/counters are active.
Program Counter is stopped.
ALE and PSEN# signals at a
HIGH level during Idle. All
registers remain unchanged.
CLK is stopped.
On-chip SRAM and SFR data
is maintained. ALE and
PSEN# signals at a LOW
level during power-down.
External Interrupts are only
active for level sensitive
interrupts, if enabled.
State of MCU
65
11.2 Power-down Mode
The power-down mode is entered by setting the PD bit in
the PCON register. In the power-down mode, the clock is
stopped and external interrupts are active for level sensitive
interrupts only. SRAM contents are retained during power-
down, the minimum V
The device exits power-down mode through either an
enabled external level sensitive interrupt or a hardware
reset. The start of the interrupt clears the PD bit and exits
power-down. Holding the external interrupt pin low restarts
the oscillator, the signal must hold low at least 1024 clock
cycles before bringing back high to complete the exit. Upon
interrupt signal restored to logic V
routine program execution resumes beginning at the
instruction immediately following the instruction which
invoked power-down mode. A hardware reset starts the
device similar to power-on reset.
To exit properly out of power-down, the reset or external
interrupt should not be executed before the V
restored to its normal operating voltage. Be sure to hold
V
the oscillator to restart and stabilize (normally less than
10 ms).
DD
voltage long enough at its normal operating level for
Enabled interrupt or hardware reset.
Start of interrupt clears IDL bit and exits idle mode,
after the ISR RETI instruction, program resumes
execution beginning at the instruction following the
one that invoked idle mode. A user could consider
placing two or three NOP instructions after the
instruction that invokes idle mode to eliminate any
problems. A hardware reset restarts the device
similar to a power-on reset.
Enabled external level sensitive interrupt or hardware
reset. Start of interrupt clears PD bit and exits power-
down mode, after the ISR RETI instruction program
resumes execution beginning at the instruction follow-
ing the one that invoked power-down mode. A user
could consider placing two or three NOP instructions
after the instruction that invokes power-down mode to
eliminate any problems. A hardware reset restarts the
device similar to a power-on reset.
DD
level is 2.0V.
Exited by
IH,
the interrupt service
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DD
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