VRS51C1100-40-Q-ISPV2 Cypress Semiconductor, VRS51C1100-40-Q-ISPV2 Datasheet - Page 10

• Manufacturer Part Number: VRS51C1100-40-Q-ISPV2
• Description: 8-bit Microcontrollers - MCU 128K+1K 40MHz 5V
• Manufacturer: Cypress Semiconductor

Specifications of VRS51C1100-40-Q-ISPV2

• Product Category: 8-bit Microcontrollers - MCU
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Operating Supply Voltage: 4.5 V to 5.5 V
• Package / Case: QFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 128 B
• Interface Type: UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 96
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

IAP Page Erase Function
By using the IAP feature, it is possible to perform a
page erase of the VRS51C1100 program or data Flash
memory (note that the memory area occupied by the
ISP boot program cannot be page erased). Each page
is 512 bytes in size.
To perform a Flash page erase, the page address is
specified by the XY (hex) value written into the
IAPFADHI register. (The value 00h must be written into
the IAPFADLO registers.)
If the “Y” portion of the IAPFADHI register represents
an even number, the page that will be erased
corresponds to the range XY00h to X(Y+1)FFh.
If the “Y” portion of the IAPFADHI register represents
an odd number, the page that will be erased
corresponds to the range X(Y-1)00h to XYFFh.
The following program example demonstrates how to
erase the page corresponding to the address B000h-
CFFFh in the program memory zone:
;** Erase Flash Program page located at address B000h to CFFFh.
PageErase: MOV
The following example shows how to erase the same
page in the data Flash memory zone:
;** Erase Flash Data page located at address B000h to CFFFh.
PageErase: MOV
IAP Chip Erase Function
The IAP chip erase function will erase the entire Flash
memory contents with the exception of the ISP boot
program
automatically unprotect the Flash memory.
IAP Chip Protect Function
When the chip protect function is enabled, values read
back from Flash memory will be 00h.
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VRS51C1100
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
area.
IAPFDATA,#55H
IAPFDATA,#0AAH
IAPFDATA,#55H
SYSCON,#04H
IAPFADHI, #0B0h
IAPFADLO,#00h
IAPFCTRL,#82H
IAPFDATA,#55H
IAPFDATA,#0AAH
IAPFDATA,#55H
SYSCON,#0CH
IAPFADHI, #0B0h
IAPFADLO,#00h
IAPFCTRL,#A2H
Running
this
;Sequence to Enable Writing
; the IAPSTART bit
;Enable IAP
;Set MSB of Page address to erase
;Set LSB of address = 00
;Set the IAP Start Bit
;Sequence to Enable Writing
; the IAPSTART bit
;Enable IAP + Data Flash
;Set MSB of Page address to erase
;Set LSB of address = 00
;Set The IAP Start bit + FZONE bit
function
will
also
ISP/AIP operation Durations
The following table shows the duration of the ISP/IAP
operations for an oscillator clock of 40MHz.
All ISP/IAP operations require a supply voltage of 5V
to be executed properly.
Program Status Word Register
The PSW register is a bit addressable register that
contains the status flags (CY, AC, OV, P), user flag
(F0) and register bank select bits (RS1, RS0) of the
8051 processor.
T
ABLE
Bit
7
6
5
4
3
2
1
0
RS1
CY
7
0
0
1
1
Operation
Byte Program
Page Erase
Chip Erase
Chip Protect
12: P
ROGRAM
Mnemonic
CY
AC
F0
RS1
RS0
OV
-
P
AC
6
RS0
0
1
0
1
S
TATUS
F0
5
W
Description
Carry Bit
Auxiliary Carry Bit from bit 3 to 4.
User definer flag
R0-R7 Registers bank select bit 0
R0-R7 Registers bank select bit 1
Overflow flag
-
Parity flag
ORD
RS1
4
Active Bank
R
EGISTER
RS0
0
1
2
3
3
(PSW) - SFR DO
OV
2
(Fosc = 40MHz)
Max Duration
400us
H
10ms
30us
3sec
page 10 of 50
Address
00h-07h
08h-0Fh
10h-17h
18-1Fh
1
-
0
P