VRS51C1100-40-Q-ISPV2 Cypress Semiconductor, VRS51C1100-40-Q-ISPV2 Datasheet

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... Versa 8051 MCU with 128KB of IAP/ISP Flash Overview The VRS51C1100 is based on the standard 8051 microcontroller architecture and is a pin compatible drop-in replacement for the 8051. The VRS51C1100 is aimed at a diversity of applications that require a large amount of program/data memory with non-volatile data storage and/or code/field based firmware upgrade capability comprehensive peripheral support ...

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... Bit 3 of Port 1 PWM2 O PWM Channel 2 6 P1.4 I/O Bit 4 of Port PWM3/ RES 10 36 RXD/P3.0 11 VRS51C1100 35 P4 PLCC-44 TXD/P3 #INT0/P3 #INT1/P3 T0/P3 T1/P3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 #EA P4 ...

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... VRS51C1100 VRS51C1100 DIP40 Pin Descriptions T 2: VRS51C1100 P D DIP40 ABLE IN ESCRIPTIONS FOR DIP40 Name I Timer 2 Clock Out 1 P1.0 I/O Bit 0 of Port 1 T2EX I Timer 2 Control 2 P1.1 I/O Bit 1 of Port 1 PWM0 O PWM Channel 0 3 P1.2 I/O Bit 2 of Port 1 PWM1 O PWM Channel 1 4 P1.3 I/O Bit 3 of Port 1 ...

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... VRS51C1100 Instruction Set The following table describes the VRS51C1100 instruction set. The instructions are function and binary code compatible with industry standard 8051s ABLE EGEND FOR NSTRUCTION ET ABLE Symbol Function A Accumulator Rn Register R0-R7 Direct Internal register address @Ri Internal register pointed (except MOVX) ...

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... VRS51C1100 Special Function Registers (SFR) Addresses 80h to FFh of the SFR address space can be accessed in direct addressing mode only. The following table lists the VRS51C1100 special function registers (SFR) ABLE PECIAL UNCTION EGISTERS SFR SFR Bit 7 Register Adrs P0 80h - SP 81h ...

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... ISP Flash memory zone from being inadvertently erased, which can happen when Flash Erase operations are performed under the control of the ISP boot program prevent the VRS51C1100 Flash memory from being read back using a parallel programmer Erase operation is performed using a parallel programmer, the entire Flash memory, including the ISP Boot program memory zone, will be erased ...

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... VRS51C1100 An alternate way to force the VRS51C1100 to jump to the ISP boot program is to maintain pins P2.6 and P2.7 or pin P4 low logic level during a hardware reset, as shown in the diagram below VRS51C1100 A ISP IGURE LTERNATE BOOT PROGRAM ACCESS 10ms P2.7 P2.6 RES OR... 10ms P4.3 RES The ISP boot program can also be accessed via the LJMP instruction ...

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... VRS51C1100 VRS51C1100 IAP feature The VRS51C1100 IAP feature allows the processor to self-program its program and data Flash memory from within the user program. Five SFR registers serve to control the IAP operation. The description of these registers is provided below. System Control Register The system control register controls the activation of the data Flash and the expanded RAM and serves to monitor the watchdog timer status ...

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... IAP feature. See the following program example: IAP_PROG: MOV IAP Byte Program in the VRS51C1100 Data Flash The IAP byte program function can also be used to program a byte into a specified data Flash memory location under the control of the IAP feature. See the ...

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... VRS51C1100 IAP Page Erase Function By using the IAP feature possible to perform a page erase of the VRS51C1100 program or data Flash memory (note that the memory area occupied by the ISP boot program cannot be page erased). Each page is 512 bytes in size. To perform a Flash page erase, the page address is specified by the XY (hex) value written into the IAPFADHI register ...

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... Data can be placed manually on the stack by using the PUSH and POP functions. Data Memory The VRS51C1100 has 1KB of on-chip RAM: 256 bytes are configured like the internal memory structure of a standard 8052, while the remaining 768 bytes can be accessed using external memory addressing (MOVX) ...

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... VRS51C1100 MOVX @DPTR instruction, but is limited as a read function. The MPAGE register default setting is 00h. T 13: MPAGE (MPAGE) - SFR 85 ABLE REGISTER MPAGE[7:0] Data Bank Control Register The DBANK register enables the data bank select function to map the entire contents of the RAM ...

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... Power Down mode is via a hardware reset (note that the watchdog timer is stopped in Power Down). When the VRS51C1100 is in Power Down, its current consumption drops to about 50uA. The SMOD bit of the PCON register controls the oscillator divisor applied to Timer 1 when used as a baud rate generator for the UART. Setting this bit to 1 doubles the UART’ ...

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... The presence of the pull-up resistance, even when the I/O’s are configured as inputs, means that a small current is likely to flow from the VRS51C1100 I/O’s pull-up resistors to the driving circuit when the inputs are driven low. For this reason, the VRS51C1100 I/O ports P1, P2, P3 and P4 are called “quasi bi- directional”. Structure of Port 0 The internal structure shown in the next figure ...

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... P0.0 Port 2 Port P2 is similar to ports 1 and 3, the difference being that P2 is used to drive the A8-A15 lines of the address bus when the EA line of VRS51C1100 is held low at reset time or when a MOVX instruction is executed. Like the P0, P1 and P3 registers, the P2 register is bit addressable. T 18: P ...

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... VRS51C1100 Auxiliary Port 1 Functions The Port 1 I/O pins are shared with the PWM outputs, Timer 2 EXT and T2 inputs, as shown below: Pin Mnemonic Function P1.0 T2 Timer 2 counter input P1.1 T2EX Timer 2 Auxiliary input P1.2 P1.3 PWM0 output PWM0 P1.4 PWM1 PWM1 output P1.5 PWM2 PWM2 output P1.6 PWM3 output PWM3 P1 ...

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... VRS51C1100 Port 4 Port 4 has four related I/O pins and its port address is located at 0D8H (P4) - SFR D8 ABLE ORT Unused P4.3 Bit Mnemonic Description 7 Unused - 6 Unused - 5 Unused - 4 Unused - 3 P4.3 Used to output the setting to pins P4.3, 2 P4.2 P4.2, P4.1, P4.0 respectively. 1 P4.1 0 P4.0 Software Port Control Some instructions allow the user to read the logic state of the output pin, while others allow the user to read the contents of the associated port register ...

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... Doing so will likely make the low-level output voltage specifications and affect device reliability. The VRS51C1100 I/O ports are not designed to source current. VRS51C1100 Timers The VRS51C1100 includes three 16-bit timers: Timer 0, Timer 1 and Timer 2. The Timers can operate in two modes: ...

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... VRS51C1100 Timer 0, Timer 1 Counter / Timer Functions Timing Function When Timer 1 or Timer 0 is configured to operate as a timer, its value is automatically incremented at every machine cycle. Once the timer value rolls over, a flag is raised and the counter acquires a value of zero. The overflow flags (TF0 and TF1) are located in the TCON register ...

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... VRS51C1100 Mode 0 A schematic representation of this mode of operation is presented in the figure below. In Mode 0, the timer operates as a 13-bit counter made LSBs of the TLx register and the 8 upper bits of the THx register. When an overflow causes the value of the register to rollover to 0, the TFx interrupt signal goes to 1. The count value is validated as soon as TRx goes to 1 and the GATE bit when INTx is 1 ...

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... VRS51C1100 Timer 2 Timer 2 of the VRS51C1100 is a 16-bit timer/counter and is similar to timers 0 and 1 in that it can operate as either an event counter or a timer. This is controlled by the C/T2 bit in the T2CON special function register. Timer 2 has three operating modes: Auto-Load, Capture, and Baud Rate Generator. These modes are selected via the T2CON ...

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... F 16: T IGURE F OSC T2 pin T2EX pin UART Serial Port The serial port on the VRS51C1100 can operate in full duplex simultaneously.) This occurs at the same speed if one TL2 TH2 timer is assigned as the clock source for both transmission and reception, and at different speeds if ...

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... H UART Operating Modes The VRS51C1100’s serial port can operate in four RB8 TI RI different modes. In all four modes, a transmission is initiated by an instruction that uses the SBUF register as a destination register. In Mode 0, reception is initiated by setting and REN incoming start bit initiates reception in the other modes, provided that REN is set to 1 ...

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... VRS51C1100 UART Transmission in Mode 0 Any instruction that uses SBUF as a destination register may initiate a transmission. The “write to SBUF” signal also loads a 1 into the 9 transmit shift register and informs the TX control block to begin a transmission. The internal timing is such that one full machine cycle will elapse between a write to SBUF instruction and the activation of SEND ...

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... VRS51C1100 UART Transmission in Mode 1 Transmission in this mode is initiated by any instruction that makes use of SBUF as a destination th register. The 9 bit position of the transmit shift register is loaded by the “write to SBUF” signal. This event also flags/informs the TX control unit that a transmission has been requested. ...

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... VRS51C1100 In Mode 2, the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency IGURE ERIAL ORT ODE LOCK IAGRAM Internal Bus 1 Write to SBUF Q S Fosc/2 SBUF D CLK ZERO DETECTOR ÷ Shift Stop SMOD Start TX Control Unit ÷16 TX Clock TI ÷16 ...

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... VRS51C1100 UART in Mode 2 and 3: Additional Information As mentioned previously, for an operation in modes 2 and 3, 11 bits are transmitted (through TXD) or received (through RXD). The signal is comprised of: a logical low Start bit, 8 data bits (LSB first programmable 9 data bit and a logical high Stop bit. ...

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... VRS51C1100 UART Baud Rates In Mode 0, the baud rate is fixed and can be represented by the following formula: Mode 0 Baud Rate = Oscillator Frequency In Mode 2, the baud rate depends on the value of the SMOD bit in the PCON SFR. From the formula below, we can see that if SMOD = 0 (which is the value on reset), the baud rate is 1/32 the oscillator frequency ...

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... VRS51C1100 The following formula can be used to calculate the baud rate in modes 1 and 3 using Timer 2: Modes 1, 3 Baud Rate = Oscillator Frequency 32x[65536 – (RCAP2H, RCAP2L)] The formula below is used to define the reload value written into the RCAP2h, RCAP2L registers to achieve a given baud rate. ...

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... D0h 1200bps A0h 300bps - Timer 2 Reload Value in Modes 1 & 3 for UART Baud Rate The following are examples of [RCAP2H, RCAP2L] reload values for Timer 2 when it is used as a baud rate generator for the VRS51C1100 UART: 22.184MHz 16.000MHz 230400bps FFFDh 115200bps FFFAh 57600bps ...

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... VRS51C1100 Interrupts The VRS51C1100 has 8 interrupt sources (9 if the WDT is included) and 7 interrupt vectors (including reset) used for handling. The interrupts are enabled via the IE register shown below –SFR A8 ABLE NTERRUPT NABLE EGISTER ET2 ES ET1 ...

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... Interrupt Enable and Interrupt Priority When the VRS51C1100 is initialized, all interrupt sources are inhibited by the bits of the IE register being reset necessary to start by enabling the interrupt sources that the application requires.This is achieved by setting bits in the IE register, as discussed previously ...

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... VRS51C1100 Modifying the Order of Priority The VRS51C1100 allows the user to modify the natural priority of the interrupts. The order can be modified by programming the bits in the IP (Interrupt Priority) register. When any bit in this register is set gives the corresponding source priority over interrupts ...

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... VRS51C1100 T 37: WDT T P ABLE IMEOUT ERIOD AT WDTPS [2:0] WDT Period 000 2.05ms 001 4.10ms 010 8.19ms 011 16.38ms 100 32.77ms 101 65.54ms 110 131.07ms 111 262.14ms To enable the WDT, the user must set bit 7 (WDTE) of the WDTCTRL register to 1. The 16-bit counter will ...

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... VRS51C1100 Pulse Width Modulation (PWM) The Pulse Width Modulation (PWM) module consists of four outputs. Each output uses an 8-bit PWM data register (PWMD) to set the number of continuous pulses within a PWM frame cycle. PWM Function Description: Each 8-bit PWM output incorporates an 8-bit register that consists of a 5-bit PWM (5 MSBs) and a 3-bit (LSBs) narrow pulse generator (NP) ...

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... VRS51C1100 PWM Data Registers The following tables describe the PWM data registers. The PWMDx bits hold the content of the PWM data register and determine the duty cycle of the PWM output waveforms. The NPx[2:0] bits will insert narrow pulses into the 8-PWM-cycle frame. ...

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... VRS51C1100 Example of PWM Timing Diagram MOV PWMD0 #83H MOV PWME, #08H F 22: PWM T D IGURE IMING IAGRAM 1st Cycle 2nd Cycle frame frame 32T 32T 16 1T (Narrow pulse inserted by NP0[2:0]=3) PWM clock= 1/T= Fosc / 2^(PDIV+1) The SPWM output cycle frame frequency = SPWM clock/32 = [Fosc/2^(PDIV+1)]/32 If Fosc = 20MHz, PDCK[1:0] of PWMC = #03H, then PWM clock = 20MHz/2^4 = 20MHz/ ...

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... VRS51C1100 Crystal consideration The crystal connected to the VRS51C1100 oscillator input should parallel type, operating in fundamental mode. The following table provides suggested capacitor and resistor feedback values for different operating frequencies. Valid for VRS51C1100 XTAL 3MHz 6MHz 9MHz ...

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... VRS51C1100 Operating Conditions T 44 ABLE PERATING ONDITIONS Symbol Description TA Operating temperature TS Storage temperature VCC5 Supply voltage Fosc 40 Oscillator Frequency DC Characteristics T 45 ABLE HARACTERISTICS Symbol Parameter VIL1 Input Low Voltage VIL2 Input Low Voltage VIH1 Input High Voltage VI H2 Input High Voltage ...

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... VRS51C1100 AC Characteristics T 46 ABLE HARACTERISTICS Symbol Parameter T LHLL ALE Pulse Width T AVLL Address Valid to ALE Low T LLAX Address Hold after ALE Low T LLIV ALE Low to Valid Instruction In T LLPL ALE Low to #PSEN low T PLPH #PSEN Pulse Width T PLIV #PSEN Low to Valid Instruction In ...

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... VRS51C1100 Data Memory Read Cycle Timing The following timing diagram provides Data Memory Read Cycle timing information IGURE ATA EMORY EAD YCLE IMING T12 T1 T2 OSC 1 ALE #PSEN #RD PORT2 INST in Float PORT0 ______________________________________________________________________________________________ www.ramtron.com ...

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... VRS51C1100 Program Memory Read Cycle Timing The following timing diagram provides Program Memory Read Cycle timing information IGURE ROGRAM EMORY EAD YCLE T12 T1 OSC 1 ALE #PSEN #RD,#WR PORT2 PORT0 ______________________________________________________________________________________________ www.ramtron.com ADDRESS A15- ...

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... VRS51C1100 Data Memory Write Cycle Timing The following timing diagram provides Data Memory Write Cycle timing information IGURE ATA EMORY RITE YCLE IMING T12 T1 T2 OSC 1 ALE #PSEN #WR PORT2 INST in Float PORT0 ______________________________________________________________________________________________ www.ramtron.com ADDRESS A15-A8 ...

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... VRS51C1100 I/O Ports Timing The following timing diagram provides Port Timing information. F 27: I IGURE ORTS IMING T7 X1 Inputs P0,P1 Inputs P2,P3 Output by Mov Current Data Px, Src RxD at Serial Port Shift Clock Mode 0 ______________________________________________________________________________________________ www.ramtron.com T8 T9 T10 T11 T12 T1 Sampled Sampled Sampled ...

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... VRS51C1100 Timing Requirement of the External Clock (VSS = 0v is assumed IGURE IMING EQUIREMENT OF XTERNAL LOCK Vdd - 0.5V 70% Vdd 20% Vdd-0.1V 0.45V External Program Memory Read Cycle The following timing diagram provides External Program Memory Read Cycle timing information ...

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... VRS51C1100 External Data Memory Read Cycle The following timing diagram provides External Data Memory Read Cycle timing information IGURE XTERNAL ATA EMORY EAD YCLE #PSEN ALE #RD TAVLL PORT 0 From Ri or DPL PORT 2 ______________________________________________________________________________________________ www.ramtron.com TLLDV TRLRH TLLYL TRLDV ...

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... VRS51C1100 External Data Memory Write Cycle The following timing diagram provides External Data Memory Write Cycle timing information IGURE XTERNAL ATA EMORY RITE YCLE #PSEN ALE TLHLL #WR TAVLL PORT 0 From Ri or DPL PORT 2 . ______________________________________________________________________________________________ www.ramtron.com TLLYL TWLWH TQVWX ...

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... VRS51C1100 Plastic Chip Carrier (PLCC-44) VRS51C1100 PLCC- Note: 1. Dimensions D & not include interlead Flash. 2. Dimension B1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inch 4. General appearance spec should be based on final visual inspection spec. ______________________________________________________________________________________________ www.ramtron.com ...

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... VRS51C1100 Plastic Quad Flat Package (QFP-44) VRS51C1100 QFP- Note: 1. Dimensions D1 and E1 do not include mold protrusion. 2. Allowance protrusion is 0.25mm per side. 3. Dimensions D1 and E1 do not include mold mismatch and are determined datum plane. 4. Dimension b does not include dambar protrusion. ...

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... VRS51C1100-40-QG VRS51C1100-40-PG VRS51C1100 Ordering Options (With ISPV2 Firmware preprogrammed) Device Number Flash Size VRS51C1100-40-L-ISPV2 VRS51C1100-40-Q-ISPV2 VRS51C1100-40-P-ISPV2 VRS51C1100-40-LG-ISPV2 VRS51C1100-40-QG-ISPV2 VRS51C1100-40-PG-ISPV2 Disclaimers Right to make change - Ramtron reserves the right to make changes to its products - including circuitry, software and services - without notice at any time ...