CY7C1512AV18-200BZXC Cypress Semiconductor Corp, CY7C1512AV18-200BZXC Datasheet - Page 19

• Manufacturer Part Number: CY7C1512AV18-200BZXC
• Description: IC SRAM 72MBIT 200MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1512AV18-200BZXC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 72M (4M x 18)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power Up Sequence in QDR-II SRAM
QDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations. During
Power Up, when the DOFF is tied HIGH, the DLL gets locked
after 1024 cycles of stable clock.
Power Up Sequence
■
■
Power Up Waveforms
Document #: 001-06984 Rev. *C
Apply power with DOFF tied HIGH (All other inputs can be
HIGH or LOW)
❐
❐
Provide stable power and clock (K, K) for 1024 cycles to lock
the DLL.
Apply V
Apply V
V
DD
/
DOFF
V
DD
DDQ
DDQ
before V
K
K
before V
DDQ
REF
or at the same time as V
Unstable Clock
Clock Start (Clock Starts after
V
DD
/
V
REF
DDQ
V
Stable (< +/- 0.1V DC per 50ns )
DD
/
V
DLL Constraints
■
■
■
DDQ
DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t
The DLL functions at frequencies down to 120 MHz.
If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid DLL locking provide 1024 cycles
stable clock to relock to the desired clock frequency.
Fix High (or tied to V DDQ )
> 1024 Stable clock
Stable)
CY7C1510AV18, CY7C1525AV18
CY7C1512AV18, CY7C1514AV18
Start Normal
Operation
KC Var
Page 19 of 28
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