CY7C1512AV18-200BZXC Cypress Semiconductor Corp, CY7C1512AV18-200BZXC Datasheet

CY7C1512AV18-200BZXC

Manufacturer Part Number

CY7C1512AV18-200BZXC

Description

IC SRAM 72MBIT 200MHZ 165TFBGA

Manufacturer

Cypress Semiconductor Corp

Datasheets

1.CY7C1514AV18-167BZXC.pdf (28 pages)

2.CY7C1512AV18-200BZXC.pdf (26 pages)

3.CY7C1512AV18-200BZXC.pdf (24 pages)

4.CY7C1514AV18-200BZXI.pdf (28 pages)

Specifications of CY7C1512AV18-200BZXC

Format - Memory

RAM

Memory Type

SRAM - Synchronous, QDR II

Memory Size

72M (4M x 18)

Speed

200MHz

Interface

Parallel

Voltage - Supply

1.7 V ~ 1.9 V

Operating Temperature

0°C ~ 70°C

Package / Case

165-TFBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C1512AV18-200BZXC

Manufacturer:

Cypress Semiconductor Corp

Quantity:

10 000

Company:

Meier Automation Equipment Co., Limited

Part Number:

CY7C1512AV18-200BZXC

Manufacturer:

CYPRESS/赛普拉斯

Quantity:

20 000

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Features

■

Selection Guide

Cypress Semiconductor Corporation

Document #: 001-06984 Rev. *E

Maximum Operating Frequency

Maximum Operating Current

Separate independent Read and Write Data Ports

❐

250 MHz Clock for high Bandwidth

2-word Burst on all Accesses

Double Data Rate (DDR) Interfaces on both Read and Write

Ports (data transferred at 500 MHz) at 250 MHz

Two Input Clocks (K and K) for precise DDR Timing

❐

Two Input Clocks for Output Data (C and C) to minimize Clock

Skew and Flight Time mismatches

Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

Systems

Single Multiplexed Address Input Bus latches Address Inputs

for both Read and Write Ports

Separate Port Selects for Depth Expansion

Synchronous Internally Self-timed Writes

QDR

Lock Loop (DLL) is enabled

Operates as a QDR I device with one Cycle Read Latency in

DLL Off Mode

Available in x 18, and x 36 Configurations

Full Data Coherency, providing Most Current Data

Core V

Available in 165-Ball FBGA Package (15 x 17 x 1.4 mm)

Offered in both Pb-free and non Pb-free Packages

Variable Drive HSTL Output Buffers

JTAG 1149.1 compatible Test Access Port

Delay Lock Loop (DLL) for Accurate Data Placement

Supports concurrent transactions

SRAM uses rising edges only

II operates with 1.5 Cycle Read Latency when Delay

= 1.8V (±0.1V); I/O V

Description

DDQ

x18

x36

= 1.4V to V

•

198 Champion Court

250 MHz

1100

250

900

72-Mbit QDR

Configurations

CY7C1512AV18 – 4M x 18

CY7C1514AV18 – 2M x 36

Functional Description

The

Synchronous Pipelined SRAMs, equipped with QDR II archi-

tecture. QDR II architecture consists of two separate ports: the

read port and the write port to access the memory array. The

read port has dedicated data outputs to support read operations

and the write port has dedicated data inputs to support write

operations. QDR II architecture has separate data inputs and

data outputs to completely eliminate the need to ‘turnaround’ the

data bus that exists with common I/O devices. Access to each

port is through a common address bus. Addresses for read and

write addresses are latched on alternate rising edges of the input

(K) clock. Accesses to the QDR II read and write ports are

completely independent of one another. To maximize data

throughput, both read and write ports are equipped with DDR

interfaces. Each address location is associated with two 18-bit

words (CY7C1512AV18), or 36-bit words (CY7C1514AV18) that

burst sequentially into or out of the device. Because data can be

transferred into and out of the device on every rising edge of both

input clocks (K and K and C and C), memory bandwidth is

maximized while simplifying system design by eliminating bus

turnarounds.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

200 MHz

200

800

900

•

CY7C1512AV18,

San Jose

CA 95134-1709

167 MHz

Burst Architecture

and

167

800

750

II SRAM 2-Word

CY7C1514AV18

CY7C1512AV18

CY7C1514AV18

Revised August 24, 2009

•

408-943-2600

MHz

Unit

are

1.8V

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